DS92UT16TUF Datasheet, PDF (21/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

11.0 Cell/Frame Delineation and
Descrambler Operation (Continued)
Note that depending on the length of the TC and the length
of the TC Header it may be necessary to word slip after a
predefined number of HEC calculations in order to obtain a
correct HEC.
C_PRESYNC — In C_PRESYNC, if a correct HEC is found
DELTA consecutive times then the state machine moves to
the C_SYNC state and the system has achieved TC delin-
eation. If an erred HEC is detected during the C_PRESYNC
state, the process moves back to the C_HUNT state.
C_SYNC — In the C_SYNC state, TC delineation is as-
sumed to be lost if an erred HEC is obtained on ALPHA
consecutive occasions. The state machine will move back to
the C_HUNT state.
The values of DELTA and ALPHA are programmable inde-
pendently for Port A and Port B. They are contained in the
RACDT and RBCDT registers (Section 18.36 RECEIVE
PORT A CELL DELINEATION THRESHOLDS — 0x40
RACDT and Section 18.55 RECEIVE PORT B CELL DELIN-
EATION THRESHOLDS — 0x80 RBCDT). On reset, DELTA
= 8 and ALPHA = 7.
11.2 FRAME DELINEATION
Once the system has achieved TC delineation, the Frame
delineation process can begin. The Frame delineation pro-
cess is achieved by checking for correct HEC’s with the
added coset x⁶ + x⁴ + x² + 1. This added coset differentiates
‘Start of Frame’ TC HEC’s from normal TC HEC’s. Only the
HEC of TC0 has this added coset.
This is the standard coset which may be added to all HEC’s
(CDIS bit in the LKSC register in Section 18.8 LINK STATUS
AND CONTROL — 0x08 LKSC). If the coset is already
added to all HEC’s, then it is added again to the HEC of TC0.
This ensures that the HEC of TC0 can always be differenti-
ated from that of other TC’s.
The Frame delineation state diagram is shown in Figure 13.
FIGURE 13. State Diagram for Frame Delineation
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F_HUNT — On reset, the Frame delineation state machine
starts in the F_HUNT state and Frame delineation has not
been achieved. Each received HEC is monitored to deter-
mine if it has the added coset and is therefore the Start Of
Frame (SOF) HEC. When a single correct SOF HEC is
detected, the state machine enters the F_PRESYNC state.
F_PRESYNC — In the F_PRESYNC state if a correct SOF
HEC is found SIGMA consecutive times the state machine
moves to the F_SYNC state and the system is said to have
achieved Frame delineation. If an errored SOF HEC is de-
tected during the F_PRESYNC state the state machine
moves back to the F_HUNT state.
F_SYNC — In the F_SYNC state, Frame delineation will be
assumed to be lost if an erred SOF HEC is obtained on MU
consecutive occasions. The state machine will move back to
the F_HUNT state.
The values of SIGMA and MU are programmable indepen-
dently for Port A and Port B. They are contained in the
RAFDT and RBFDT registers (Section 18.37 RECEIVE
PORT A FRAME DELINEATION THRESHOLDS — 0x41
RAFDT and Section 18.56 RECEIVE PORT B FRAME DE-
LINEATION THRESHOLDS — 0x81 RBFDT). On reset,
SIGMA = 8 and MU = 7.
11.3 DESCRAMBLER OPERATION
Once TC delineation has been obtained, the Descrambler
synchronization can begin.
After reset, the Descrambler expects the far-end transmitting
device to send it’s Scrambler sequence embedded in Idle
cells so that the Descrambler can synchronize (lock) to it.
This scrambler-sequence transfer is achieved by means of
the Remote Descrambler Loss of Lock bit (RDSLL) in the
Remote Alarm and Signalling byte (Section 6.3.7.1 Remote
Alarm and Signaling Byte). This received bit is stored as the
RARDSLL bit of the RARA register for Port A (Section 18.33
RECEIVE PORT A REMOTE STATUS AND
ALARMS — 0x3C RARA) and the RBRDSLL bit of the RBRA
register for Port B (Section 18.52 RECEIVE PORT B RE-
MOTE STATUS AND ALARMS — 0x7C RBRA).
The lock status of the Descrambler is transmitted to the
far-end device as the RDSLL bit. If the Descrambler is out of
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