DS92UT16TUF Datasheet, PDF (57/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
• PSI[3:0] When in lock this is the threshold that the descrambler confidence counter must reach to lose descrambler lock.
When in lock the descrambler confidence counter increments on incorrect HEC predictions and decrements on good HEC
predictions.
• RHO[3:0] When out of lock this is the threshold that the descrambler confidence counter must reach to gain descrambler lock.
When out of lock the descrambler confidence counter decrements on incorrect HEC predictions and increments on good HEC
predictions.
18.39 RECEIVE PORT A BIT ERROR COUNT — 0x43 to 0x45 RABEC2 to RABEC0
RABEC2 0x43
RABEC1 0x44
RABEC0 0x45
7
RABEC2[7]
RABEC1[7]
RABEC0[7]
6
RABEC2[6]
RABEC1[6]
RABEC0[6]
TABLE 59. RABEC2–RABEC0
5
RABEC2[5]
RABEC1[5]
RABEC0[5]
4
RABEC2[4]
RABEC1[4]
RABEC0[4]
3
RABEC2[3]
RABEC1[3]
RABEC0[3]
2
RABEC2[2]
RABEC1[2]
RABEC0[2]
1
RABEC2[1]
RABEC1[1]
RABEC0[1]
0
RABEC2[0]
RABEC1[0]
RABEC0[0]
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The RABEC2, RABEC1 and RABEC0 registers contain the Port A received bit error count whenever the RABEC bit of the RACTL
register is set. If the RABEC bit of the RACTL register is clear these registers are cleared.
• RABEC2–RABEC0 This register must be read in the order of most significant byte RABEC2 first and least significant byte
RABEC0 last, or the value read will not be valid. This counter will not roll-over from 0xFFFFFF to 0x000000 but will stick at
0xFFFFFF.
18.40 RECEIVE PORT B LINK LABEL — 0x60 RBLL
7
RBLL[7]
6
RBLL[6]
5
RBLL[5]
TABLE 60. RBLL
4
RBLL[4]
3
RBLL[3]
2
RBLL[2]
1
RBLL[1]
0
RBLL[0]
Type:
Read only
Software Lock: No
Reset Value: 0x00
The Receive Port B Link Label register contains the Link Trace Label byte received in TC6 on receive Port B. Whenever the
received link label changes value, the RBLLC alarm bit in the RBLA register is set, which will raise an interrupt if the
corresponding interrupt enable bit is set.
• RBLL[7:0] Port B Received Link Trace Label byte contents.
18.41 RECEIVE PORT B EXPECTED LINK LABEL — 0x61 RBELL
7
RBELL[7]
6
RBELL[6]
5
RBELL[5]
TABLE 61. RBELL
4
RBELL[4]
3
RBELL[3]
2
RBELL[2]
1
RBELL[1]
0
RBELL[0]
57
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