DS92UT16TUF Datasheet, PDF (63/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
• PSI[3:0] When in lock this is the threshold that the descrambler confidence counter must reach to lose descrambler lock.
When in lock the descrambler confidence counter increments on incorrect HEC predictions and decrements on good HEC
predictions.
• RHO[3:0] When out of lock this is the threshold that the descrambler confidence counter must reach to gain descrambler lock.
When out of lock the descrambler confidence counter decrements on incorrect HEC predictions and increments on good HEC
predictions.
18.58 RECEIVE PORT B BIT ERROR COUNT — 0x83 to 0x85 RBBEC2 to RBBEC0
RBBEC2 0x83
RBBEC1 0x84
RBBEC0 0x85
7
RBBEC2[7]
RBBEC1[7]
RBBEC0[7]
6
RBBEC2[6]
RBBEC1[6]
RBBEC0[6]
TABLE 78. RBBEC2–RBBEC0
5
RBBEC2[5]
RBBEC1[5]
RBBEC0[5]
4
RBBEC2[4]
RBBEC1[4]
RBBEC0[4]
3
RBBEC2[3]
RBBEC1[3]
RBBEC0[3]
2
RBBEC2[2]
RBBEC1[2]
RBBEC0[2]
1
RBBEC2[1]
RBBEC1[1]
RBBEC0[1]
0
RBBEC2[0]
RBBEC1[0]
RBBEC0[0]
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The RBBEC2, RBBEC1 and RBBEC0 registers contain the Port B received bit error count whenever the RBBEC bit of the RBCTL
register is set. If the RBBEC bit of the RBCTL register is clear, these registers are cleared.
• RBBEC2–RBBEC0 This register must be read in the order of most significant byte RBBEC2 first and least significant byte
RBBEC0 last, or the value read will not be valid. This counter will not roll-over from 0xFFFFFF to 0x000000 but will stick at
0xFFFFFF.
18.59 UTOPIA CONFIGURATION — 0xA0 UCFG
7
Reserved
6
Reserved
5
CLVM[1]
TABLE 79. UCFG
4
CLVM[0]
3
BWIDTH
2
Reserved
1
UBDEN
0
UMODE
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x00
The UTOPIA Configuration register defines the UTOPIA interface operating modes. The default is ATM Layer Level 2 mode (31
ports) using CLAV0 with16 bit data.
• CLVM[1:0] Clav Mode bits. 00 = Up to 31 ports using CLAV0, 01 or 10 = Reserved, 11 = Up to 248 ports using CLAV0 to
CLAV7.
• BWIDTH UTOPIA data bus width. Set = 8-bit data bus and Clear = 16-bit mode.
• UBDEN UTOPIA Bidirectional pins enable. Set = the UTOPIA bidirectional pins take on the functionality as defined by the
UMODE setting. Clear = All UTOPIA interface bidirectional pins are tri-stated. This is to avoid pin contention at the UTOPIA
pins on reset.
• UMODE UTOPIA ATM or PHY mode. Set = PHY Layer interface and Clear = ATM Layer Interface.
18.60 UTOPIA CONNECTED PORT LIST — 0xA1 to 0xA4 UCPL3 to UCPL0
UCPL3 0xA1
UCPL2 0xA2
UCPL1 0xA3
UCPL0 0xA4
7
Reserved
UCPL2[7]
UCPL1[7]
UCPL0[7]
6
UCPL3[6]
UCPL2[6]
UCPL1[6]
UCPL0[6]
TABLE 80. UCPL1–UCPL0
5
UCPL3[5]
UCPL2[5]
UCPL1[5]
UCPL0[5]
4
UCPL3[4]
UCPL2[4]
UCPL1[4]
UCPL0[4]
3
UCPL3[3]
UCPL2[3]
UCPL1[3]
UCPL0[3]
2
UCPL3[2]
UCPL2[2]
UCPL1[2]
UCPL0[2]
1
UCPL3[1]
UCPL2[1]
UCPL1[1]
UCPL0[1]
0
UCPL3[0]
UCPL2[0]
UCPL1[0]
UCPL0[0]
Type:
Read/Write
Software Lock: Yes
Reset Value: 0xFF, except UCPL3 = 0x7F
The UCPL3, UCPL2, UCPL1 and UCPL0 registers define the connected UTOPIA ports for polling. The sub-ports present for the
connected ports is defined in the UCSPL register. Note that at least one port has to be connected for correct polling to occur, so
these registers should never be set to all zeroes. See Section 8.0 UTOPIA Interface Operation. If no ports are required then use
of the Configuration Traffic inhibit functionality is recommended. See Section 10.0 Configuration and Traffic Inhibit Operation.
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