DS92UT16TUF Datasheet, PDF (49/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
ETXD2 0x12
ETXD1 0x13
ETXD0 0x14
7
ETXD2[7]
ETXD1[7]
ETXD0[7]
6
ETXD2[6]
ETXD1[6]
ETXD0[6]
TABLE 33. ETXD7–ETXD0 (Continued)
5
4
3
ETXD2[5]
ETXD2[4]
ETXD2[3]
ETXD1[5]
ETXD1[4]
ETXD1[3]
ETXD0[5]
ETXD0[4]
ETXD0[3]
2
ETXD2[2]
ETXD1[2]
ETXD0[2]
1
ETXD2[1]
ETXD1[1]
ETXD0[1]
0
ETXD2[0]
ETXD1[0]
ETXD0[0]
Type:
Read/Write
Software Lock: No
Reset Value: 0x00
The ETXD7, ETXD6, ETXD5, ETXD4, ETXD3, ETXD2, ETXD1 and ETXD0 registers contain the ECC message to be transmitted.
• ETXD7–ETXD0 When the ETXBR bit is set, then these registers have full read/write access to allow flexible assembly of the
ECC message before initiating transmission by setting the ETXSD bit. When the ETXBR is clear during message transmis-
sion, these registers are read only so that the message being transmitted cannot be overwritten and corrupted.
18.14 GENERAL PURPOSE INPUT OUTPUT — 0x15 GPIO
7
DDR[3]
6
DDR[2]
5
DDR[1]
TABLE 34. GPIO
4
DDR[0]
3
IO[3]
2
IO[2]
1
IO[1]
0
IO[0]
Type:
Bits [7:4] Read/Write
Bits[3:0] are Read Only when GPIO[3:0] are defined as Inputs, and Read/Write when GPIO[3:0] are defined as
Outputs.
Software Lock: No
Reset Value: 0xF0
The General Purpose Input/Output register controls the four general purpose input/output pins GPIO[3:0].
• DDR[3:0] The Data Direction bits DDR[3:0] define the function of the GPIO[3:0] pins. When a DDR bit is set the corresponding
GPIO pin is an input and when the DDR bit is clear the corresponding GPIO pin is an output.
• IO[3:0] The IO bits reflect the value of the GPIO pins. When defined as an output by the DDR bit, then the IO bit value is driven
out on the corresponding GPIO pin. When defined as an input by the DDR bit, then the IO bit value captures the incoming
value on the corresponding GPIO pin.
18.15 TEST ERROR CONTROL — 0x16 TERRCTL
7
EBRST[3]
6
EBRST[2]
5
EBRST[1]
TABLE 35. TERRCTL
4
EBRST[0]
3
ERFHEC
2
ERCHEC
1
ERBIP
0
TXPRBS
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x00
The Test Error Control register is used to control the transmission of a PRBS pattern for Bit Error Rate testing, or to introduce HEC
and BIP errors so that the Cell Delineation, Frame Delineation, Descrambler Lock and performance monitoring functions can be
tested. This is a test register and should not be used on live traffic. The exact nature of the errored HEC and BIP bytes is
determined by the ERRBIP1, ERRBIP0 and ERRHEC registers.
• EBRST[3:0] The Error Burst bits EBRST[3:0] define the number of consecutive erred HEC’s and/or BIP’s to be generated and
transmitted.
• ERFHEC The Error Frame HEC bit, when set, will cause EBRST consecutive Frame HEC’s to be erred. When this has been
completed the hardware will clear this bit.
• ERCHEC The Error Cell HEC bit, when set, will cause EBRST consecutive Cell HEC’s to be erred. When this has been
completed the hardware will clear this bit.
• ERBIP The Error BIP bit, when set, will cause EBRST consecutive BIP’s to be erred. When this has been completed the
hardware will clear this bit.
• TXPRBS Transmit PRBS pattern. When set, the transmit section sends the raw scrambler pseudo-random sequence
(polynomial x³¹ + x²⁸ + 1). No data is transmitted. The TCS Assembler will be paused and no cells will be read from the FIB
queue. The far end receiver can lock to this PRBS pattern to count bit errors if the RABEC/RBBEC bit is set in the
RACTL/RBCTL register. This is not a live traffic test.
18.16 ERROR BIP MASK — 0x17 to 0x18 ERRBIP1 to ERRBIP0
49
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