DS92UT16TUF Datasheet, PDF (23/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

11.0 Cell/Frame Delineation and
Descrambler Operation (Continued)
or start-up until it receives the cleared RDSLL bit in the
Remote Alarm and Signaling byte. After TC delineation oc-
curs at the receive end, the DS92UT16 will count correct
scrambler sequence predictions until it matches the confi-
dence counter (default setting is RHO = 8). When the correct
number of scrambler sequence predictions matches the con-
fidence counter, the descrambler is synchronized and the
receiving DS92UT16 clears the RDSLL bit.
In this example, the time it takes for a receiving DS92UT16
to synchronize to the transmitting DS92UT16, after the PLL
locks, is approximately determined by the following calcula-
tion. This time will differ according to PDU length and the
value programmed as the confidence thresholds.
(1+8) TC = 9 (34 cycles) = 306 cycles for TC sync, and (1+8)
(1 frame) = 9 (1904 cycles) = 17136 cycles. This is a total of
17442 cycles and assumes that the descrambler lock occurs
during the 8 frames it takes for the frame delineation to
occur.
12.0 LVDS Interface Operation
The LVDS interface combines a transmit serializer and two
receive deserializers. The serializer accepts 16- bit data from
the TCS Assembler block and transforms it into a serial data
stream with embedded clock information. Each deserializer
recovers the clock and data from the received serial data
stream to deliver the resulting 16-bit wide words to the
corresponding TCS DisAssembler block.
The LVDS interface has a Transmit serializer block and two
Receive deserializer blocks that can operate independent of
each other. The transmit data is duplicated over two differ-
ential output pairs with independent tri-state controls. The
transmit block has a power-down control. Each receiver has
a power down control and the two output stages have inde-
pendent tri-state control. These features enable efficient op-
eration in various applications.
The serializer and deserializer blocks each have three oper-
ating states. They are the Initialization, Data Transfer, and
Resynchronization states. In addition, there are two passive
states: Powerdown and TRI-STATE.
The following sections describe each operating mode and
passive state. For clarity these descriptions refer only to the
receive Port A. The operation of receive Port B is the same.
12.1 INITIALIZATION
Before the DS92UT16 sends or receives data, it must initial-
ize the links to and from another DS92UT16. Initialization
refers to synchronizing the Serializer’s and the Deserializer’s
PLL’s to local clocks. The local clocks must be the same
frequency or within a specified range if from different
sources. After the Serializers synchronize to the local clocks,
the Deserializers synchronize to the Serializers as the sec-
ond and final initialization step.
Step 1: After applying V_CC and GND to the Serializer and
Deserializer, the LVDS transmit outputs are held in TRI-
STATE and the on-chip power-sequencing circuitry disables
the internal circuits. When V_CC reaches V_CCOK (2.2V) in
each device, the PLL in the serializer and deserializer begins
locking to the local clock. In the Serializer, the local clock is
the LVDS_TxClk, while in the Port A Deserializer it is the
reference clock, LVDS_ARefClk. A local on-board oscillator
or other source provides the specified clock input to the
LVDS_TxClk and LVDS_ARefClk pins.
The Serializer outputs remain in TRI-STATE until the PLL
locks to the LVDS_TxClk. After locking to LVDS_TxClk, the
Serializer block is now ready to send data or synchronization
patterns. If the LVDS_Synch pin is high, or the TXSYNC bit
of the LVC register is set (see Section 18.4 LVDS
CONTROL — 0x04 LVC), then the Serializer block generates
and sends the synchronization patterns (sync-pattern).
The internal Port A Deserializer data outputs remain invalid
while the PLL locks to the reference clock.
When the Port A Deserializers PLL locks to incoming data or
sync-pattern on the LVDS_ADin pins, it will clear the corre-
sponding Local Loss Of Signal bit, LLOSA, in the ETXRXA
register (see Section 18.10 ECC TRANSMIT BUFFER AND
RECEIVE LVDS ALARMS — 0x0A ETXRXA) and the lock
pin LVDS_ALock_n will go low.
Step 2: The Deserializer PLL must synchronize to the Seri-
alizer to complete the initialization. The Serializer that is
generating the stream to the Deserializer must send random
(non-repetitive) data patterns or sync-patterns during this
step of the Initialization State. The Deserializer will lock onto
sync-patterns within a specified amount of time. The lock to
random data depends on the data patterns and, therefore,
the lock time is unspecified.
In order to lock to the incoming LVDS data stream, the
Deserializer identifies the rising clock edge in a sync-pattern
and will synchronize to the embedded clock in less than 5 µs.
If the Deserializer is locking to a random data stream from
the Serializer, then it performs a series of operations to
identify the rising clock edge and locks to it. Because this
locking procedure depends on the data pattern, it is not
possible to specify how long it will take. At the point where
the Port A Deserializer’s PLL locks to the embedded clock,
the LVDS_ALock_n pin goes low, the LLOSA bit of the
ETXRXA register may be cleared and valid data is presented
to the TCS DisAssembler block. Note that the
LVDS_ALock_n signal is synchronous to valid data being
presented to the TCS DisAssembler.
The user’s application determines whether sync-patterns or
lock to random data is the preferred method for synchroni-
zation. If sync-patterns are preferred, the associated Port A
deserializer’s LVDS_ALock_n pin is a convenient way to
provide control of the LVDS_Synch pin, possibly via the
RARLOSA (Receive Port A, Remote Loss Of Signal) bit of
the RARA register, see Section 18.33 RECEIVE PORT A
REMOTE STATUS AND ALARMS — 0x3C RARA.
12.2 DATA TRANSFER
After initialization, the Serializer is able to transfer data to the
Deserializer. The serial data stream includes a start bit and
stop bit appended by the serializer, which frame the sixteen
data bits. The start bit is always high and the stop bit is
always low. The start and stop bits also function as clock bits
embedded in the serial stream.
The Serializer block accepts 16-bit data from the TCS As-
sembler block. The internal version of the LVDS_TxClk sig-
nal latches the incoming data. If the LVDS_Synch input or
the TXSYNC bit of the LVC register is high for 5 LVDS_TxClk
cycles, the Serializer does not latch data from the TCS
Assembler block.
The Serializer transmits the data and clock bits (16+2 bits) at
18 times the LVDS_TxClk frequency. For example, if
LVDS_TxClk is 50 MHz, the serial rate is 50 X 18 =
900 Mbps. Since only 16 bits are from input data, the serial
“payload’’ rate is 16 times the LVDS_TxClk frequency. For
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