DS92UT16TUF Datasheet, PDF (14/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

7.0 Signal Description (Continued)
TABLE 11. Pin Description (Continued)
Note 2: These pins are Outputs in ATM Layer mode and Inputs PHY Layer mode.
Note 3: These pins are only used in PHY layer mode, Extended 248 PHY mode. In Normal 31 PHY mode or ATM layer mode, they must be unconnected.
Note 4: In PHY layer mode this is the Utopia TxClk and in ATM layer mode this is the Utopia RxClk.
Note 5: In PHY layer mode this is the Utopia RxClk and in ATM layer mode this is the Utopia TxClk.
8.0 UTOPIA Interface Operation
This section describes the operation of the UTOPIA Interface
of the DS92UT16. The UTOPIA interface mode of operation
is defined in the UTOPIA Configuration (UCFG) register
described
in
Section
18.59
UTOPIA
CONFIGURATION — 0xA0 UCFG. The format of the PDU
cells carried over this interface is defined in the PDU Con-
figuration (PDUCFG) register described in Section 18.5 PDU
CONFIGURATION — 0x05 PDUCFG.
The interface can operate in ATM layer mode or PHY layer
mode. When operating as a Level 2 ATM layer interface, the
protocol can be extended to cope with up to 248 PHY ports
rather than the maximum 31 allowed by the standard Level 2
definition. This Extended Level 2 mode is achieved with
eight CLAV and eight ENB signals.
On power up the device defaults to ATM layer mode. To
prevent potential contention on the Utopia interface signals,
all the Utopia pins which are bidirectional are configured as
outputs in tri-state mode and the Utopia interface block is
disabled. The user must select the device operating mode,
ATM layer or PHY layer, by writing the appropriate value to
the UMODE bit of the UCFG register before enabling the
Utopia interface block and releasing the Utopia interface
pins. Enabling the Utopia interface and releasing the Utopia
pins is achieved by setting the UBDEN bit of the UCFG
register.
8.1 UTOPIA BASIC LEVEL 2 MODE - 31 PORTS
(Default Mode)
In UTOPIA Level 2 mode:
• 8-bit or 16-bit data buses are controlled by the BWIDTH
bit of the UCFG register. In 8-bit mode only
U_TxData[7:0] and U_RxData[7:0] are valid; parity is cal-
culated and checked only over these bits of the data
buses and the upper bits of the data buses are not used.
In 16-bit mode of the full U_TxData[15:0] and
U_RxData[15:0] are valid and parity is calculated over all
bits of the data buses.
• One ATM Layer can communicate with up to 31 PHY
ports using the MPhy address busses U_TxAddr[4:0] and
U_RxAddr[4:0] and the control signals U_TxCLAV[0],
U_RxCLAV[0], U_TxENB[0] and U_RxENB[0].
• U_TxCLAV[7:1], U_RxCLAV[7:1], U_TxENB[7:1] and
U_RxENB[7:1] are not used.
• All Queues from 30 to 0 of the MTB may be used. There
is one queue for each MPhy address so the use of the
queues will depend on the connected ports list defined by
the UCPL3–UCPL0 registers.
• Uses the connected ports list defined by the UCPL3-
UCPL0 registers. In ATM mode, these registers are used
to determine the ports that should be polled. In PHY
mode, these registers are used to determine which MPhy
addresses the device should respond to during polling.
• The connected sub-port list defined in the UCSPL regis-
ter is not used.
• The sub-port address location defined by USPAL and
USPAM registers is not used.
• The CLAV mode bits CLVM[1:0] of the UCFG register
should be defined as CLVM[1:0] = 00.
The configuration of the inputs/outputs of the UTOPIA Level
2 interface for ATM Layer mode and PHY Layer mode is
shown in Figure 8. The main difference is that in ATM mode
the CLAV pins are inputs and the MPhy Address and ENB
pins are outputs; whereas in PHY mode, the CLAV pins are
outputs and the MPhy Address and ENB pins are inputs.
Note that in ATM Layer mode the DS92UT16 does not
generate the UTOPIA clocks and must be supplied with
these clocks just as in PHY mode.
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