DS92UT16TUF Datasheet, PDF (66/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
MTBQF3 0xD0
MTBQF2 0xD1
MTBQF1 0xD2
MTBQF0 0xD3
7
Reserved
MTBQF2[7]
MTBQF1[7]
MTBQF0[7]
6
MTBQF3[6]
MTBQF2[6]
MTBQF1[6]
MTBQF0[6]
TABLE 87. MTBQF3–MTBQF0
5
MTBQF3[5]
MTBQF2[5]
MTBQF1[5]
MTBQF0[5]
4
MTBQF3[4]
MTBQF2[4]
MTBQF1[4]
MTBQF0[4]
3
MTBQF3[3]
MTBQF2[3]
MTBQF1[3]
MTBQF0[3]
2
MTBQF3[2]
MTBQF2[2]
MTBQF1[2]
MTBQF0[2]
1
MTBQF3[1]
MTBQF2[1]
MTBQF1[1]
MTBQF0[1]
0
MTBQF3[0]
MTBQF2[0]
MTBQF1[0]
MTBQF0[0]
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x00
The MTBQF3, MTBQF2, MTBQF1 and MTBQF0 registers allow each of the queues to be flushed. Flushing a queue removes all
PDU cells from the queue. The processor sets the appropriate bit in the MTBQF register to flush a queue. When this has been
completed, the hardware will clear the bit. So after setting a bit to flush a queue, the processor should poll the MTBQF register
to determine when the flushing has been completed.
• MTBQF3–MTBQF0 MTBQF3[6] corresponds to queue 31 and MTBQF0[0] corresponds to queue 0. When a bit is set, then
a flush of the corresponding queue is initiated and when the queue flush is completed and the queue is now in normal
operation.
18.68 MTB CELL FLUSH — 0xD4 to 0xD7 MTBCF3 to MTBCF0
MTBCF3 0xD4
MTBCF2 0xD5
MTBCF1 0xD6
MTBCF0 0xD7
7
Reserved
MTBCF2[7]
MTBCF1[7]
MTBCF0[7]
6
MTBCF3[6]
MTBCF2[6]
MTBCF1[6]
MTBCF0[6]
TABLE 88. MTBCF3–MTBCF0
5
MTBCF3[5]
MTBCF2[5]
MTBCF1[5]
MTBCF0[5]
4
MTBCF3[4]
MTBCF2[4]
MTBCF1[4]
MTBCF0[4]
3
MTBCF3[3]
MTBCF2[3]
MTBCF1[3]
MTBCF0[3]
2
MTBCF3[2]
MTBCF2[2]
MTBCF1[2]
MTBCF0[2]
1
MTBCF3[1]
MTBCF2[1]
MTBCF1[1]
MTBCF0[1]
0
MTBCF3[0]
MTBCF2[0]
MTBCF1[0]
MTBCF0[0]
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x00
The MTBCF3, MTBCF2, MTBCF1 and MTBCF0 registers allow the PDU cell at the head of each of the queues to be flushed. This
removes the PDU cell from the head of the queue without corrupting the queue. The processor sets the appropriate bit in the
MTBCF register to flush a cell from a queue. When this has been completed, the hardware will clear the bit. So after setting a bit
to flush a cell from a queue, the processor should poll the MTBCF register to determine when the flush has been completed.
• MTBCF3–MTBCF0 MTBCF3[6] corresponds to queue 31 and MTBCF0[0] corresponds to queue 0. When a bit is set, then a
flush of the PDU cell at the head of the queue is initiated and when clear, the cell flush is completed and the queue is now in
normal operation.
18.69 QUEUE FLUSH — 0xD8 QFL
7
Reserved
6
Reserved
5
Reserved
TABLE 89. QFL
4
Reserved
3
Reserved
2
Reserved
1
FIBFL
0
MTBFL
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x00
The Queue Flush register allows both the MTB and the FIB queues to be completely flushed. This removes all PDU cells from
either the MTB or FIB queue. The processor sets the appropriate bit in the QFL register to flush a queue. When this has been
completed, the hardware will clear the bit. So after setting a bit to flush a queue the processor should poll the QFL register to
determine when the flush has been completed.
• FIBFL When set, then a flush of the FIB queue is initiated and when clear, the FIB queue flush is completed and the queue
is now in normal operation.
• MTBFL When set, then a flush of the MTB queue is initiated and when clear, the MTB queue flush is completed and the queue
is now in normal operation.
18.70 MTB QUEUE OVERFLOW — 0xD9 to 0xDC MTBQOV3 to MTBQOV0
www.national.com
66