DS92UT16TUF Datasheet, PDF (58/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
Type:
Read/Write
Software Lock: No
Reset Value: 0x00
The Receive Port B Expected Link Label register defines the expected contents of the Link Trace Label byte received in TC6 on
receive Port B. If the actual received value, as stored in the RBLL register is not the same as the expected value defined here
the RBLLM alarm bit in the RBLA register is set, which may raise a processor interrupt if the corresponding interrupt enable is set.
• RBELL[7:0] Port B Expected Received Link Trace Label byte contents.
18.42 RECEIVE PORT B LOCAL ALARMS — 0x62 RBLA
7
Reserved
6
RBLLC
5
RBLLM
TABLE 62. RBLA
4
RBLCS
3
RBLDSLL
2
RBLTCLL
1
RBLFLL
0
ERBBF
Type:
Bits[6:1] Read only/Clear on Read
Bit[0] Read/Write
Software Lock: No
Reset Value: 0x00
The Receive Port B Local Alarms register contains information on the status of the Port B disassembler. When set, RBLLC,
RBLLM, RBLDSLL, RBLTCLL, and RBLFLL will raise an interrupt if the corresponding interrupt enable bits are set. Also, a change
in value on RBLDSLL, RBLTCLL and RBLFLL will set the RBLCS bit, which will raise an interrupt if the corresponding interrupt
enable bit is set.
• RBLLC Receive Port B, Local Link Label Change of Status. Set = Change in RBLL register value.
• RBLLM Receive Port B, Local Link Label Mismatch. Set = Received link label RBLL different than expected link label RBELL.
• RBLCS Receive Port B, Local Change of Status. Set = change in value of RBLDSLL, RBLTCLL or RBLFLL bits.
• RBLDSLL Receive Port B, Local Descrambler Loss of Lock. Set = Out of Lock and Clear = Lock.
• RBLTCLL Receive Port B, Local Transport Container Delineation Loss of Lock. Set = Out of Lock and Clear = Lock.
• RBLFLL Receive Port B, Local Frame Delineation Loss of Lock. Set = Out of Lock and Clear = Lock.
The ERBBF register bit indicates that the ECC receive section for Port B has successfully received a full ECC message consisting
of the 8 data bytes contained in registers ERBD7–ERBD0 and a the message can now be read by the processor.
On reset, the ERBBF will be clear indicating no valid message has been received. When a valid message is received and stored
in the ERBD7–ERBD0 data registers, the ERBBF bit will be set and will raise an interrupt if the corresponding interrupt enable
bit is set. Therefore, the processor can detect a received message on the interrupt or by polling the ERBBF bit. When the
processor has finished reading the message from the ERBD7–ERBD0 data registers and is ready to receive a new message, it
simply clears the ERBBF bit. When a full message has been successfully received, this is communicated to the far-end device
via the ECC signalling.
• ERBBF The ERBBF bit, when set, indicates that ERBD7–ERBD0 data registers contain a full valid received message. The
data in the ERBD7–ERBD0 data registers cannot be overwritten with a new received message while ERBBF is set. When
ERBBF is cleared, this allows the ERBD7–ERBD0 data registers to be overwritten with a new received message.
18.43 RECEIVE PORT B LOCAL INTERRUPT ENABLES — 0x63 RBLIE
7
Reserved
6
RBLLCIE
5
RBLLMIE
TABLE 63. RBLIE
4
RBLCSIE
3
RBLSLLIE
2
RBLTCLLIE
1
RBLFLLIE
0
ERBBFIE
Type:
Read/Write
Software Lock: No
Reset Value: 0x00
This register contains the interrupt enables for the alarms in the RBLA register. Set = interrupt enabled and Clear = interrupt
disabled.
18.44 RECEIVE PORT B CONTROL — 0x64 RBCTL
7
Reserved
6
Reserved
5
Reserved
TABLE 64. RBCTL
4
Reserved
3
RBESS
2
RBBEC
1
RBDFLK
0
RBCDIS
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