DS92UT16TUF Datasheet, PDF (67/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
MTBQOV3
0xD9
MTBQT29
0xDA
MTBQOV1
0xDB
MTBQOV0
0xDC
7
Reserved
6
MTBQOV3[6]
TABLE 90. MTBQOV3–MTBQOV0
5
4
3
MTBQOV3[5] MTBQOV3[4] MTBQOV3[3]
2
MTBQOV3[2]
1
MTBQOV3[1]
0
MTBQOV3[0]
MTBQOV2[7] MTBQOV2[6] MTBQOV2[5] MTBQOV2[4] MTBQOV2[3] MTBQOV2[2] MTBQOV2[1] MTBQOV2[0]
MTBQOV1[7] MTBQOV1[6] MTBQOV1[5] MTBQOV1[4] MTBQOV1[3] MTBQOV1[2] MTBQOV1[1] MTBQOV1[0]
MTBQOV0[7] MTBQOV0[6] MTBQOV0[5] MTBQOV0[4] MTBQOV0[3] MTBQOV0[2] MTBQOV0[1] MTBQOV0[0]
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The MTBQOV3, MTBQOV2, MTBQOV1 and MTBQOV0 registers indicate the overflow status of the thirty-one queues in the
MTB. If a queue has filled to its threshold defined in the MTBQT31–MTBQT0 registers, and an attempt is made to write another
cell to the queue, then the overflow bit for that queue will be set in these registers. These bits reflect that an attempt has been
made to write to an already full queue and may be used as an indication of problems with the Flow Control mechanism. Up to
seven additional cells will be accepted into the queue before a hard overflow occurs. Once the threshold value plus seven cells
has been exceeded any additional cells will be rejected and discarded automatically. A subsequent read of a cell from the specific
queue out over the Utopia interface will be successful, and will clear the overflow bit in this register once the number of cells in
the queue is below the threshold. If any bit in the MTBQOV3–MTBQOV0 registers is set then the MTBSOVA bit of the UAA
register will be set and may raise an interrupt.
• MTBQOV3–MTBQOV0 MTBQOV3[6] corresponds to queue 31 and MTBQOV0[0] corresponds to queue 0. When a bit is set,
then there was an attempt to overflow the corresponding queue.
18.71 ATM DOWN2UP LOOPBACK CELL COUNT — 0xE0 D2ULBCC
TABLE 91. D2ULBCC
7
6
5
4
3
2
1
0
D2ULBCC[7] D2ULBCC[6] D2ULBCC[5] D2ULBCC[4] D2ULBCC[3] D2ULBCC[2] D2ULBCC[1] D2ULBCC[0]
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The ATM Down2Up Loopback Cell Count register counts the number of outgoing loopback cells detected on the UTOPIA interface
when Down2Up loopback is enabled with the D2ULB bit of the ALBC register, see Section 18.18 ATM AND LVDS LOOPBACK
CONTROL — 0x1A ALBC. Note that this counter is only incremented when a loopback cell is read out of the device.
• D2ULBCC[7:0] Down2Up Loopback Cell Count value. This register will not roll-over from 0x00 to 0xFF but will stick at 0xFF.
18.72 UTOPIA AND ATM ALARMS — 0xE1 UAA
7
PDULA
6
CTFRA
5
D2ULBC
TABLE 92. UAA
4
U2DLBC
3
UPRTY
2
FIBOVA
1
MTBSOVA
0
MTBHOVA
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The UTOPIA and ATM Alarms register monitors the UTOPIA interface, loopbacks and queue overflows. When set these bits will
raise an interrupt if the corresponding interrupt enables are set.
• PDULA PDU Length Alarm bit. Set = PDU length as defined by the PDUCFG register is greater than the maximum PDU cell
length of 64 bytes. Clear = PDU length is less than or equal to maximum of 64 bytes.
• CTFRA Cell Transfer Alarm bit. This alarm is only valid when the device is configured as a PHY layer by setting the UMODE
bit of the UCFG register. It indicates that the controlling ATM layer device has caused an incorrect cell transfer to or from the
DS92UT16. An incorrect cell transfer can only occur when a suspended cell transfer is restarted with an different MPhy
address than initially selected. Set = Incorrect cell transfer has occurred on the UTOPIA transmit or receive interface.
• D2ULBC Set = D2ULBCC count register has changed value.
• U2DLBC Set = RAU2DLBC or RBU2DLBC count registers have changed value.
• UPRTY Set = A parity error has occurred on an incoming ATM cell byte.
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