DS92UT16TUF Datasheet, PDF (52/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
Type:
Read only
Software Lock: No
Reset Value: 0x00
The Receive Port A Expected Link Label register defines the expected contents of the Link Trace Label byte received in TC6 on
receive Port A. If the actual received value, as stored in the RALL register is not the same as the expected value defined here the
RALLM alarm bit in the RALA register is set, which may raise a processor interrupt if the corresponding interrupt enable is set.
• RAELL[7:0] Port A Expected Received Link Trace Label byte contents.
18.23 RECEIVE PORT A LOCAL ALARMS — 0x22 RALA
7
Reserved
6
RALLC
5
RALLM
TABLE 43. RALA
4
RALCS
3
RALDSLL
2
RALTCLL
1
RALFF
0
ERABF
Type:
Bits[6:1] Read only/Clear on Read
Bit[0] Read/Write
Software Lock: No
Reset Value: 0x00
The Receive Port A Local Alarms register contains information on the status of the Port A disassembler. When set RALLC,
RALLM, RALDSLL, RALTCLL and RALFLL will raise an interrupt if the corresponding interrupt enable bits are set. Also a change
in value on RALDSLL, RALTCLL or RALFLL will set the RALCS bit which will raise an interrupt if the corresponding interrupt
enable bit is set.
• RALLC Receive Port A, Local Link Label Change of Status. Set = Change in RALL register value.
• RALLM Receive Port A, Local Link Label Mismatch. Set = Received link label RALL different than expected link label RAELL.
• RALCS Receive Port A, Local Change of Status. Set = change in value of RALDSLL, RALTCLL or RALFLL bits
• RALDSLL Receive Port A, Local Descrambler Loss of Lock. Set = Out of Lock and Clear = Lock.
• RALLTCLL Receive Port A, Local Transport Container Delineation Loss of Lock. Set = Out of Lock and Clear = Lock.
• RALFLL Receive Port A, Local Frame Delineation Loss of Lock. Set = Out of Lock and Clear = Lock.
The ERABF register bit indicates that the ECC receive section for Port A has successfully received a full ECC message consisting
of the 8 data bytes contained in registers ERAD7–ERAD0, and the message can now be read by the processor.
On reset, the ERABF will be clear indicating no valid message has been received. When a valid message is received and stored
in the ERAD7–ERAD0 data registers, the ERABF bit will be set and will raise an interrupt if the corresponding interrupt enable
bit is set. Therefore, the processor can detect a received message on the interrupt or by polling the ERABF bit. When the
processor has finished reading the message from the ERAD7–ERAD0 data registers and is ready to receive a new message it
simply clears the ERABF bit. When a full message has been successfully received this is communicated to the far-end device via
the ECC signalling.
• ERABF The ERABF bit, when set, indicates that ERAD7–ERAD0 data registers contain a full valid received message. The
data in the ERAD7–ERAD0 data registers cannot be overwritten with a new received message while ERABF is set. When
ERABF is cleared this allows the ERAD7–ERAD0 data registers to be overwritten with a new received message.
18.24 RECEIVE PORT A LOCAL INTERRUPT ENABLES — 0x23 RALIE
7
Reserved
6
RALLCIE
5
RALLMIE
TABLE 44. RALIE
4
RALCSIE
3
RALDSLLIE
2
RALTCLLIE
1
RALFLLIE
0
ERABFIE
Type:
Read/Write
Software Lock: No
Reset Value: 0x00
This register contains the interrupt enables for the alarms in the RALA register. Set = interrupt enabled and Clear = interrupt
disabled.
18.25 RECEIVE PORT A CONTROL — 0x24 RACTL
7
Reserved
6
Reserved
5
Reserved
TABLE 45. RACTL
4
Reserved
3
RAESS
2
RABEC
1
RADFLK
0
RACDIS
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