DS92UT16TUF Datasheet, PDF (13/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

7.0 Signal Description (Continued)
TABLE 11. Pin Description (Continued)
Signal Name
Description
Width Signal Type
Polarity
LVDS INTERFACE
LVDS_ADout[+,−]
A Serial data differential outputs.
2
LVDS_BDout[+,−]
B Serial data differential outputs.
2
LVDS_ADenb
Serial transmit data A output enable.
1
LVDS_BDenb
Serial transmit data B output enable.
1
LVDS_Synch
External control to transmit SYNCH patterns on
1
serial interface.
LVDS_TxClk
Transmit clock.
1
LVDS_TxPwdn
Transmit section power down
1
LVDS_ADin[+,−]
PortA Serial data differential inputs.
2
LVDS_ALock_n
PortA Clock recovery lock status
1
LVDS_ARxClk
PortA Recovered clock.
1
LVDS_ARefClk
PortA Reference clock for receive PLLs.
1
LVDS_APwdn
PortA Power Down.
1
LVDS_BDin[+,−]
PortB Serial data differential inputs.
2
LVDS_Block_n
PortB Clock recovery lock status.
1
LVDS_BRxClk
PortB Recovered clock.
1
LVDS_BRefClk
PortB Reference clock for receive PLLs.
1
LVDS_BPwdn
PortB Power Down.
1
CPU & GENERAL CONTROL
CPU_cs
Select signal used to validate the address bus
1
for read and write data transfers.
CPU_rd (CPU_ds) Read or Data Strobe, depending on
1
CPU_BusMode.
CPU_wr (CPU_rnw) Write or Read/Write, depending on
1
CPU_BusMode.
CPU_int
Interrupt request line.
1
CPU_Data[7:0]
Data bus.
8
CPU_Addr[7:0]
Address bus.
8
CPU_BusMode
Mode select for bus protocol.
1
GPIO [3:0]
General Purpose Input/Output.
4
Reset_n
Reset min pulse is 2X slowest clock period.
1
JTAG TEST INTERFACE
JTAG_CLK
Test clock.
1
JTAG_Reset
Test circuit reset.
1
JTAG_TMS
Test Mode Select.
1
JTAG_TDI
Test Data In.
1
JTAG_TDO
Test Data Out.
1
Test_se
SCAN enable (for manufacturing test only)
1
TOTAL PIN COUNT
Total Functional I/O
LVDS V_DD/V_SS
CV_DD/CV_SS
IOV_DD/IOV_SS
Total Power
3.3V LVDS power for analog and digital
2.5V Core Power for digital functions
3.3V I/O power ring
No Connect
No signal connected to this pin
Total Pins
196 LBGA, 15x15 mm, 1.0 mm ball pitch
Output
Output
Input
Input
Input
Active High
Active High
Active High
Input
Input
Input
Output
Output
Input
Input
Input
Output
Output
Input
Input
Active Low
Active Low
Active Low
Input
Active Low
Input
Active Low
Input
Output
BiDir
Input
Input
BiDir
Input
Active Low
(Write)
Active Low
Active Low
Input
Input
Input
Input
Output
Input
Active Low
Active High
133
46
6
8
60
3
196
Note 1: These pins are Inputs in ATM Layer mode and Outputs PHY Layer mode
Internal
Bias
Pull Up
Pull Up
Pull Down
Pull Up
Pull Up
Pull Up
Open Drain
Pull Down
Pull Up
Pull Up
Pull Up
Pull Down
13
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