DS92UT16TUF Datasheet, PDF (16/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

8.0 UTOPIA Interface Operation (Continued)
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FIGURE 9. Extended UTOPIA Level 2 UMODE Configuration
The main difference is that in ATM mode the CLAV pins are
inputs and the MPhy Address and ENB pins are outputs,
whereas in PHY mode the CLAV pins are outputs and the
MPhy Address and ENB pins are inputs. Also, in ATM mode
all eight CLAV and ENB pins are used, but in PHY mode only
one of the CLAV and ENB pins are used.
Note that in ATM Layer mode the DS92UT16 does not
generate the UTOPIA clocks but must be supplied with these
clocks just as in PHY mode.
8.2.1 ATM Polling
When configured as an ATM Layer device, the DS92UT16
polls the connected PHY ports using the MPhy address
busses U_TxAddr and U_RxAddr. Only those ports which
are connected will be polled. The connected ports list de-
fined in the UCPL3–UCPL0 registers is used to determine
which ports are connected. The PHY ports respond on
U_TxCLAV[7:0] and U_RxCLAV[7:0]. The MPhy address de-
termines the Port and the CLAV pin number determines the
sub-port. Therefore up to 8 sub-ports may be connected to a
port. Polling of a single MPhy address will get eight re-
sponses on the eight CLAV lines. The DS92UT16 uses the
connected sub-port list defined in the UCSPL register to
determine which of these eight sub-port responses are valid.
On reset, the UCPL3–UCPL0 registers are all set to 0xFF
and the UCSPL register is set to 0x01, so the DS92UT16 will
poll all ports and assume only sub-port zero is connected.
8.2.2 PHY Polling
When configured as a PHY Layer device, the DS92UT16 is
polled by the connected ATM device. During polling, the
DS92UT16 will only respond to MPhy addresses on
U_TxAddr and U_RxAddr, which are defined as connected.
The connected ports list defined in the UCPL3–UCPL0 reg-
isters is used to determine which ports are connected. On
reset the UCPL3–UCPL0 registers are all set to 0xFF so the
DS92UT16 will respond to all MPhy addresses during poll-
ing.
NOTE: There must always be at least one connected port
defined in the UCPL3–UCPL0 registers. If no ports are to be
connected then use Configuration Traffic Inhibit mode de-
scribed in Section 10.0 Configuration and Traffic Inhibit Op-
eration.
8.2.3 Sub-Port Address
The operation of the sub-port address is illustrated in Figure
10. To use the Extended Level 2 mode that allows address-
ing up to 248 Ports, the ATM Layer (that which drives the
DS92UT16 in PHY mode) must be capable of inserting a
three bit sub-port address in the PDU cell for use by the
DS92UT16. This 3-bit sub-port address must reside in either
the User Prepend, Cell Header, or UDF bytes. It’s location is
defined in the UTOPIA Sub-Port Address Location (USPAL)
and UTOPIA Sub-Port Address Mask (USPAM) registers.
The USPAL register defines which byte of the User Prepend,
Cell Header, or UDF, contains the address and the USPAM
register defines which three bits of that byte are the sub-port
address.
Transmit Path Example: The MPhy address is interpreted
as the Port address. So, a cell destined for the PHY desig-
nated as Port 0 Sub-Port 7 has the three bit sub-port address
7 (binary “111”) inserted into the defined sub-port address
location of the PDU cell by the ATM layer head-end. It is then
transmitted to the DS92UT16 in PHY mode using MPhy
address 0. The DS92UT16 in PHY mode does not examine
the sub-port address because all cells are transmitted down-
bridge anyway.
At the far end, the DS92UT16 in ATM mode extracts the
sub-port address. This is used to determine which sub-port
CLAV/ENB signals the destination PHY is connected to. A
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