DS92UT16TUF Datasheet, PDF (56/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
18.35 RECEIVE PORT A UP2DOWN LOOPBACK CELL COUNT — 0x3E RAU2DLBC
TABLE 55. RAU2DLBC
7
6
5
4
3
2
1
0
RAU2DLBC[7] RAU2DLBC[6] RAU2DLBC[5] RAU2DLBC[4] RAU2DLBC[3] RAU2DLBC[2] RAU2DLBC[1] RAU2DLBC[0]
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The Receive Port A Up2Down Loopback Cell Count register counts the number of incoming loopback cells detected from the Port
A LVDS interface when Up2Down loopback is enabled with the U2DLB bit of the ALBC register, see Section 18.18 ATM AND
LVDS LOOPBACK CONTROL — 0x1A ALBC. Note that this counter is incremented when an incoming loopback cell is received
and that this differs from the functionality of the Down2Up Loopback Cell Count register, see Section 18.71 ATM DOWN2UP
LOOPBACK CELL COUNT — 0xE0 D2ULBCC.
• RAU2DLBC[7:0] Port A Up2Down Loopback Cell Count value. This register will not roll-over from 0x00 to 0xFF but will stick
at 0xFF.
18.36 RECEIVE PORT A CELL DELINEATION THRESHOLDS — 0x40 RACDT
7
ALPHA[3]
6
ALPHA[2]
5
ALPHA[1]
TABLE 56. RACDT
4
ALPHA[0]
3
DELTA[3]
2
DELTA[2]
1
DELTA[1]
0
DELTA[0]
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x78
The Receive Port A Cell and Transport Container Delineation Thresholds register controls the operation of the Port A cell
delineation state machine. The cell delineation lock status is reflected in the RALTCLL bit of the RALA register.
• ALPHA[3:0] When in lock this is the number of consecutive incorrect cell HEC’s required to lose cell delineation lock.
• DELTA[3:0] When out of lock this is the number of consecutive correct cell HEC’s required to gain cell delineation lock.
18.37 RECEIVE PORT A FRAME DELINEATION THRESHOLDS — 0x41 RAFDT
7
MU[3]
6
MU[2]
5
MU[1]
TABLE 57. RAFDT
4
MU[0]
3
SIGMA[3]
2
SIGMA[2]
1
SIGMA[1]
0
SIGMA[0]
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x78
The Receive Port A Frame Delineation Thresholds register controls the operation of the Port A frame delineation state machine.
The frame delineation lock status is refiected in the RALFLL bit of the RALA register.
• MU[3:0] When in lock this is the number of consecutive incorrect cell HEC’s required to lose frame delineation lock.
• SIGMA[3:0] When out of lock this is the number of consecutive correct frame HEC’s required to gain frame delineation lock.
18.38 RECEIVE PORT A DESCRAMBLER LOCK THRESHOLDS — 0x42 RADSLKT
7
PSI[3]
6
PSI[2]
5
PSI[1]
TABLE 58. RADSLKT
4
PSI[0]
3
RHO[3]
2
RHO[2]
1
RHO[1]
0
RHO[0]
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x88
The Receive Port A Descrambler Lock Thresholds register controls the operation of the Port A descrambler lock state machine
confidence counter. The descrambler lock status is reflected in the RALDSLL bit of the RALA register.
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