DS92UT16TUF Datasheet, PDF (82/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

24.0 Electrical Characteristics (Continued)
Signal Name
U_UDBClk,
U_UUBClk
U_TxData[15:0],
U_TxPrty,
U_TxSOC,
U_TxEnb[7:0],
U_TxAddr[4:0]
U_TxClav [7:0]
Signal Name
U_UDBClk,
U_UUBClk
U_RxEnb[7:0],
U_RxAddr[4:0]
U_RxData[15:0],
U_RxParity,
U_RxSOC,
U_RxClav [7:0]
DIR
A→P
A→P
A←P
DIR
A→P
A→P
A←P
TABLE 97. UTOPIA Transmit Timing
Item
f1
tT2
tT3
tT4
tT5
Description
TxClk Frequency (nominal)
TxClk Duty Cycle
TxClk Peak-to-Peak Jitter
TxClk Rise/Fall Time
Input Setup to TxClk
tT6
Input Hold from TxClk
tT7
tT8
tT9
tT10
tT11
tT12
Input Setup to TxClk
Input Hold from TxClk
Signal Going Low Impedance to TxClk
Signal Going High Impedance to
TxClk (1)
Signal Going Low Impedance from
TxClk
Signal Going High Impedance from
TxClk
TABLE 98. UTOPIA Receive Timing
Item
f1
tT2
tT3
tT4
tT5
tT6
tT7
tT8
tT9
tT10
tT11
tT12
Description
RxClk Frequency (nominal)
RxClk Duty Cycle
RxClk Peak-to-Peak Jitter
RxClk Rise/Fall Time
Input Setup to RxClk
Input Hold from RxClk
Input Setup to RxClk
Input Hold from RxClk
Signal Going Low Impedance to
RxClk
Signal Going High Impedance to
RxClk (2)
Signal Going Low Impedance from
RxClk
Signal Going High Impedance from
RxClk
Min
0
40%
—
—
4 ns
1 ns
4 ns
1 ns
4 ns
0 ns
1 ns
1 ns
Min
0
40%
—
—
4 ns
1 ns
4 ns
1 ns
4 ns
0 ns
1 ns
1 ns
Max
50 MHz
60%
5%
2 ns
—
—
—
—
—
—
—
—
Max
50 MHz
60%
5%
2 ns
—
—
—
—
—
—
—
—
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