DS92UT16TUF Datasheet, PDF (48/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
The ETXBR register bit indicates that the ECC transmit section has successfully transmitted the full ECC message consisting of
the 8 data bytes contained in registers ETXD7–ETXD0 and a new message can be assembled and transmitted. This is a read
only bit that the processor must examine before assembling a new ECC message in the ETXD7–ETXD0 data registers.
If this bit is not set then any writes to ETXD7–ETXD0 will have no affect.
On reset the ETXBR will be set indicating a message can be assembled for transmission. The processor assembles a message
in the ETXD7–ETXD0 data registers. To send the message the processor simply sets the ETXSD register bit. This clears the
ETXBR bit which prevents write access to the ETXD7–ETXD0 registers so that the message cannot be overwritten. When the far
end ECC receiver indicates via the ECC signalling that the message has been received successfully, then the near end ECC
transmitter ETXSD bit is cleared and the ETXBR bit is set. The ETXBR bit, when set, may raise a processor interrupt if the
corresponding interrupt enable is set. The processor can therefore detect that a message has been successfully transmitted
either by the interrupt or by polling the ETXBR bit.
Note that the ETXBR bit cannot be cleared on a read of this register but can only be cleared by setting the ETXSD bit of the
ETXSD register.
• ETXBR The ETXBR bit, when set, indicates that the current ECC message has been successfully transmitted and a new
message can be assembled. If this bit is not set, then the current message has not been received at the far end and a new
message cannot be assembled. The ETXBR bit is cleared by the setting of the ETXSD bit. The ETXBR bit is set either by the
far end successfully receiving a message or by the processor clearing the ETXSD bit.
18.11 ECC Tx BUFFER AND Rx LVDS INTERRUPT ENABLES — 0x0B ETXRXIE
7
Reserved
6
Reserved
5
Reserved
TABLE 31. ETXRXIE
4
Reserved
3
LLOSCIE
2
LLOSAIE
1
LLOSBIE
0
ETXBRIE
Type:
Read/Write
Software Lock: No
Reset Value: 0x00
This register contains the interrupt enables for the alarms in the ETXRXA register. Set = interrupt enabled and Clear = interrupt
disabled.
18.12 ECC TRANSMIT BUFFER SEND — 0x0C ETXSD
7
Reserved
6
Reserved
5
Reserved
TABLE 32. ETXSD
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
ETXSD
Type:
Read/Write
Software Lock: No
Reset Value: 0x00
The ETXSD register bit controls the transmission of an ECC message.
• ETXSD The setting of the ETXSD bit initiates the transmission of the ECC message in the ETXD0–ETXD7 data registers, but
only if the ETXBR is also set. Once transmission of a message has been initiated in this way, it will proceed until the far end
ECC receiver indicates, via the ECC signalling, that the message has been received successfully. The ETXSD bit will be
cleared and the ETXBR register bit is set automatically when the far end ECC receiver indicates that the message has been
received successfully. To re-send the same message simply set the ETXSD bit again.
• See Section 16.0 Embedded Communication Channel Operation for a complete description of the Embedded Communication
Channel operation.
• The processor can halt transmission of a message by clearing the ETXSD bit which sets the ETXBR bit to enable a new
message to be constructed in the ETXD7–ETXD0 registers.
18.13 ECC TRANSMIT BUFFER — 0x0D to 0x14 ETXD7 to ETXD0
ETXD7 0x0D
ETXD6 0x0E
ETXD5 0x0F
ETXD4 0x10
ETXD3 0x11
7
ETXD7[7]
ETXD6[7]
ETXD5[7]
ETXD4[7]
ETXD3[7]
6
ETXD7[6]
ETXD6[6]
ETXD5[6]
ETXD4[6]
ETXD3[6]
TABLE 33. ETXD7–ETXD0
5
ETXD7[5]
ETXD6[5]
ETXD5[5]
ETXD4[5]
ETXD3[5]
4
ETXD7[4]
ETXD6[4]
ETXD5[4]
ETXD4[4]
ETXD3[4]
3
ETXD7[3]
ETXD6[3]
ETXD5[3]
ETXD4[3]
ETXD3[3]
2
ETXD7[2]
ETXD6[2]
ETXD5[2]
ETXD4[2]
ETXD3[2]
1
ETXD7[1]
ETXD6[1]
ETXD5[1]
ETXD4[1]
ETXD3[1]
0
ETXD7[0]
ETXD6[0]
ETXD5[0]
ETXD4[0]
ETXD3[0]
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