DS92UT16TUF Datasheet, PDF (24/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

12.0 LVDS Interface Operation
(Continued)
instance, if LVDS_TxClk = 50 MHz, the payload data rate is
50 X 16 = 800 Mbps. LVDS_TxClk is provided by the data
source and must be in the range of 30 MHz to 52 MHz.
When the Port A Deserializer channel synchronizes to the
input from a Serializer, it drives its LVDS_ALock_n pin low,
the LLOSA bit of the ETXRXA register is cleared and valid
data is delivered to the TCS DisAssembler. The process flow
is that the Port A Deserializer locks to the embedded clock,
uses it to generate multiple internal data strobes, and then
drives the recovered clock on the LVDS_ARxClk pin. The
LVDS_ARxClk is synchronous to the data delivered to the
TCS DisAssembler. While the LVDS_ALock_n pin is low,
data to the TCS DisAssembler is valid. Otherwise, the data is
invalid and is ignored by the TCS DisAssembler and an
interrupt may be raised on the LLOSA bit being set high.
LVDS_ALock_n and LVDS_ARxClk signals will drive a mini-
mum of three CMOS input gates, a 15 pF total load.
The Port A Deserializer input pins LVDS_ADin are high
impedance during Receiver Powerdown (LVDS_APwdn pin
low or bit RAPWDN of the LVC register set high) and power-
off (V_CC = 0V).
12.3 RESYNCHRONIZATION
Whenever the Port A Deserializer loses lock, it will automati-
cally try to resynchronize. For example, if the embedded
clock edge is not detected two times in succession, the PLL
loses lock and the LVDS_ALock_n pin and the LLOSA bit are
driven high. The Port A Deserializer then enters the operat-
ing mode where it tries to lock to a random data stream. It
looks for the embedded clock edge, identifies it and then
proceeds through the synchronization process.
The logic state of the LVDS_ALock_n pin indicates whether
the data is valid; when it is low, the data is valid. The system
must monitor the LVDS_ALock_n pin and LLOSA bit to
determine whether received data is valid. The DS92UT16
facilitates this by allowing an interrupt to be raised on LLOSA
being set. There is a short delay in response to the PLL
losing synchronization to the incoming data stream.
The user can choose to resynchronize to the random data
stream or to force fast synchronization by pulsing the Seri-
alizer LVDS_Synch pin or setting the TXSYNC bit. This
scheme is left up to the user discretion. One recommenda-
tion is to provide a feedback loop using the LVDS_ALock_n
pin itself to control the sync request of the Serializer, which is
the LVDS_Synch pin.
12.4 POWERDOWN/TRI-STATE
The Powerdown state is a very low power consuming sleep
mode that the Serializer and Deserializer will occupy while
waiting for initialization. You can also use the LVDS_ADenb,
LVDS_BDenb, LVDS_TxPwdn, LVDS_APwdn and
LVDS_BPwdn pins, or the TXPWDN, TXADEN, TXBDEN,
RAPWDN and RBPWDN bits of the LVC register to reduce
power when there are no pending data transfers. The Port A
Deserializer enters Powerdown when LVDS_APwdn is
driven low or the RAPWDN bit is set. In Powerdown, the PLL
stops and the outputs go into TRI-STATE, which reduces
supply current to the µA range.
To bring the Port A Deserializer block out of the Powerdown
state, the system drives LVDS_APwdn high and the RAP-
WDN bit is cleared. When the Deserializer exits Powerdown,
it automatically enters the Initialization state. The system
must then allow time for Initialization before data transfer can
begin.
The LVDS_TxPwdn driven low or the TXPWDN bit clear,
forces the Serializer block into low power consumption
where the supply current is in the µA range. The Serializer
PLL stops and the output goes into a TRI-STATE condition.
To bring the Serializer block out of the Powerdown state, the
system drives LVDS_TxPwdn high and sets the TXPWDN
bit. When the Serializer exits Powerdown, its PLL must lock
to the LVDS_TxClk before it is ready for the Initialization
state. The system must then allow time for Initialization
before data transfer can begin.
NOTE: The associated reference clock must always be ac-
tive for a change of state on the receiver powerdowns. That
is LVDS_ARefClk for LVDS_APwdn and LVDS_BRefClk for
LVDS_BPwdn must be active to have an effect.
12.5 LOOPBACK TEST OPERATION
The DS92UT16 includes two Loopback modes for testing
the device functionality and the transmission line continuity.
They are the Line Loopback and the Local Loopback modes.
The Line Loopback connects the serial data input
(LVDS_ADin or LVDS_BDin) to the serial data output (LVD-
S_ADout and LVDS_BDout). The input signal also routes to
the parallel data input of the TCS DisAssembler. In the Line
Loopback mode, the serial input stream goes through dese-
rializer, passes to both the DisAssembler and the serializer
inputs, and then is transmitted out onto the transmission line.
The Local Loopback connects the serial data output from the
serializer back to the serial data input of the deserializer. The
connection route includes all the functional blocks of the
DS92UT16 except for the LVDS serial output buffers and
LVDS receiver input.
The ALBC register controls the loopbacks with the LNEN,
LNSEL, LCLA and LCLB bits.
12.6 LOOP TIMING OPERATION
The DS92UT16 includes a Loop Timing mode controlled by
the LT bit of the GCS register, see Section 18.3 GENERAL
CONTROL AND STATUS — 0x03 GCS. On reset the LT bit is
clear so the LVDS transmit clock is sourced directly from the
LVDS_TxClk pin. Setting the LT bit will switch the transmit
clock to be sourced from the recovered clock of the active
receiver, as defined by the LBA bit of the LKSC register, see
Section 18.8 LINK STATUS AND CONTROL — 0x08 LKSC.
The LVDS transmit and TCA blocks will then be driven by
this internal clock and not the LVDS_TxClk pin.
Switching to or from Loop Timing mode will cause the trans-
mitted scrambler sequence to change. This will cause the far
end device to loose scrambler lock. However, it may take a
number of frames for the far end device to register the lose
of scrambler lock because of the setting of the confidence
counter, see Section 11.3 DESCRAMBLER OPERATION.
The far end device will then relock to the new scrambler
sequence and operation will resume as normal.
Also, when operating in Loop Timing mode, then a Loss of
Lock on the active LVDS receiver, or a switch of active
receiver, will also cause the transmitted scrambler sequence
to change. This again will cause the far end device to loose
scrambler lock. The far end device will then relock to the new
scrambler sequence and operation will resume as normal.
Note that from the time that the near end device is switched
to or from Loop Timing mode, until the time that the far end
device registers the loss of scrambler lock, all received data
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