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DS92UT16TUF Datasheet, PDF (72/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers
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20.0 Package (Continued)
Ball
N8
K1
K13
P10
A1
A11
D10
F7
F8
G2
G6
G7
G14
J7
J11
H6
H5
K2
J6
E9
E8
F12
E13
E10
C1
A14
A13
A9
A10
C14
E14
B10
D14
D2
A3
A4
A6
A7
C3
B1
D4
B2
E4
D1
D3
G8
J8
K8
Pin Name
DGND
DVDD25
DVDD25
DVDD25
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
GPIO [0]
GPIO [1]
GPIO [2]
GPIO [3]
JTAG_CLK
JTAG_Reset
JTAG_TDI
JTAG_TDO
JTAG_TMS
LVDS_ADen
LVDS_ADin[−]
LVDS_ADin[+]
LVDS_ADout[−]
LVDS_ADout[+]
LVDS_ALock_n
LVDS_APwdn
LVDS_ARefClk
LVDS_ARxClk
LVDS_BDen
LVDS_BDin[−]
LVDS_BDin[+]
LVDS_BDout[−]
LVDS_BDout[+]
LVDS_BLock_n
LVDS_BPwdn
LVDS_BRefClk
LVDS_BRxClk
LVDS_Synch
LVDS_TxClk
LVDS_TxPwdn
NC
NC
NC
TABLE 96. Pin Locations — BGA196 Package (Continued)
Signal Type
Description
GND
Digital GND
2.5V
2.5V
2.5V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
BiDir LVTTL
VDD for Core Logic
VDD for Core Logic
VDD for Core Logic
Digital VDD
Digital VDD
Digital VDD
Digital VDD
Digital VDD
Digital VDD
Digital VDD
Digital VDD
Digital VDD
Digital VDD
Digital VDD
General Purpose Input and Output
BiDir LVTTL
General Purpose Input and Output
BiDir LVTTL
General Purpose Input and Output
BiDir LVTTL
General Purpose Input and Output
Input LVTTL
Boundary Scan Test Clock
Input LVTTL
Boundary Scan Test Circuit Reset
Input LVTTL
Boundary Scan Test Data In
Output LVTTL
Boundary Scan Test Data Out
Input LVTTL
Boundary Scan Test Mode Select
Input LVTTL
Driver Enable for Transmit A
Diff. Input
Input for Receiver Port A
Diff. Input
Input for Receiver Port A
Diff. Output
Output for Driver A
Diff. Output
Output for Driver A
Output LVTTL
Lock Signal from Receive Port A
Input LVTTL
Receive Port A and Deserializer Power Down
Input LVTTL
Reference Clock for Receiver A PLL
Output LVTTL
Recovered Clock Output from Receive Port A
Input LVTTL
Driver Enable for Transmit B
Diff. Input
Input for Receive Port B
Diff. Input
Input for Receive Port B
Diff. Output
Output for Driver B
Diff. Output
Output for Driver B
Output LVTTL
Lock Signal from Receive Port B
Input LVTTL
Receive Port B and Deserializer Power Down
Input LVTTL
Reference Clock for Receiver B PLL
Output LVTTL
Recovered Clock Output from Receive Port B
Input LVTTL
Force SYNC patterns on Transmit A and B
Input LVTTL
Reference Clock for Driving Transmission Function
Input LVTTL
Powerdown for LVDS Serializer
NO CONNECT
NO CONNECT
NO CONNECT
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