DS92UT16TUF Datasheet, PDF (25/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

12.0 LVDS Interface Operation
(Continued)
at the far end will be corrupted. This is because the scram-
bler lock works on a frame-by-frame basis and each frame is
56 transport containers long. For this reason switching to or
from Loop Timing mode should not be carried out on live
traffic.
Note that both the input LVDS_TxClk clock and active port
recovered clock must be present for the switch to complete
successfully.
Note also that on reset the device will operate from the
LVDS_TxClk input pin clock and therefore this clock must be
present to ensure correct operation.
13.0 Switching Receive Ports
The DS92UT16 has two independent receive sections des-
ignated Port A and Port B. Either port can receive ATM cell
traffic, but only one at a time. The LBA bit of the LKSC
register, described in Section 18.8 LINK STATUS AND
CONTROL — 0x08 LKSC, controls this function.
The ECC also has two independent receive sections. This is
controlled by the settings of the ECCA and ECCB bits of the
LKSC register. Either one or both ECC receive sections can
be active. The selected ECC receive port is independent of
the active traffic port selection. For example, you may select
Port A as active for cell traffic by clearing the LBA bit, and
select the ECC to be receiving on Port B by setting the
ECCB bit. The ECC can communicate over either link with-
out affecting the active cell traffic port because the ECC does
not use any of the transport container designated for ATM
cells.
Selecting the active traffic receive port is accomplished by
simply changing the value of the LBA bit. When set high, Port
B accepts the traffic cells, and when cleared to low, Port A
accepts the traffic cells. After changing the LBA value, the
MTB will complete receiving the current cell before switching
to the new receive Port. The MTB then waits for the next
Start of Cell indication from the associated TCS DisAssem-
bler. This means that the MTB does not need to be flushed or
reset because of a change in the active traffic receive Port.
Switching from one port to another completes in a maximum
of 6 clock cycles. However, this switch does not start until
after receiving the end of the current cell into the MTB.
Changing the value of the LBA bit to switch ports will clear
the ABSC bit of the LKSC register. When the switch from one
port to the other is completed successfully then the hardware
will set the ABSC bit. The processor can poll this bit to
determine when the switch has been completed.
14.0 Performance Monitoring
14.1 LIVE TRAFFIC PERFORMANCE MONITORING
Performance monitoring is carried out on live traffic in two
ways. One is using the HEC bytes associated with each
cell’s TC. The other is the BIP bytes of the F channel
embedded in the frame structure, as described in Section
6.3.7.4 BIP16.
A 24-bit count of errored HEC’s received on Port A is con-
tained in the RAHECC2–RAHECC0 registers (Section 18.27
RECEIVE PORT A HEC COUNT — 0x2E to 0x30 RAHECC2
to RAHECC0). When the number of received erred HEC’s
exceeds the threshold defined in the RAHECT2–RAHECT0
registers (Section 18.28 RECEIVE PORT A HEC
THRESHOLD — 0x31 to 0x33 RAHECT2 to RAHECT0), an
interrupt may be raised on the RAXHEC alarm bit in the
RAPA alarm register (Section 18.31 RECEIVE PORT A PER-
FORMANCE ALARMS — 0x3A RAPA). The count register
RAHECC2–RAHECC0 is reset on read.
A 24-bit count of errored BIP bytes is similarly maintained in
the RABIPC2–RABIPC0 registers (Section 18.29 RECEIVE
PORT A BIP COUNT — 0x34 to 0x36 RABIPC2 to
RABIPC0). The associated erred BIP threshold is contained
in the RABIPT2–RABIPT0 registers (Section 18.30 RE-
CEIVE PORT A BIP THRESHOLD — 0x36 to 0x39 RABIPT2
to RABIPT0) and an interrupt may be raised on the RAXBIP
alarm bit in the RAPA alarm register. The count register
RABIPC2–RABIPC0 is also reset on read.
The same mechanism is in place for Port B using the
RBHECC2–RBHECC0, RBHECT2–RBHECT0, RBBIPC2–
RBBIPC0, RBBIPT2–RBBIPT0 and RBPA registers (Section
18.46 RECEIVE PORT B HEC COUNT — 0x6E to 0x70
RBHECC2 to RBHECC0, Section 18.47 RECEIVE PORT B
HEC THRESHOLD — 0x71 to 0x73 RBHECT2 to RBHECT0,
Section 18.48 RECEIVE PORT B BIP COUNT — 0x74 to
0x76 RBBIPC2 to RBBIPC0, Section 18.49 RECEIVE PORT
B BIP THRESHOLD — 0x77 to 0x79 RBBIPT2 to RBBIPT0
and Section 18.50 RECEIVE PORT B PERFORMANCE
ALARMS — 0x7A RBPA).
In addition to the HEC and BIP monitoring, live traffic loop-
back cell monitoring and loopback cell counts are main-
tained and may raise interrupts on detection of a loopback
cell as described in Section 15.1 ATM CELL LOOPBACK.
14.2 BIT ERROR COUNT MODE
In addition to live traffic performance monitoring, a PRBS
based LVDS link bit error count facility is available. In this
mode, no cells are transmitted and instead the raw scram-
bler pseudo-random sequence (polynomial x³¹ + x²⁸ + 1) is
transmitted. The descrambler will lock to this sequence and
then count individual bit errors in the PRBS stream. This bit
error count is maintained in a count register. As there is no
data cell delineation, the frame delineation will be lost. This
is not a live traffic test.
The device will transmit this PRBS data when the TXPRBS
bit of the TERRCTL register is set (Section 18.15 TEST
ERROR CONTROL — 0x16 TERRCTL). When this bit is set,
no cell data is transmitted and the TCS Assembler is paused.
In addition, no cells will be read from the FIB queue.
The receive section of Port A can lock onto this sequence
and maintain the bit error count when the RABEC bit of the
RACTL register is set (Section 18.25 RECEIVE PORT A
CONTROL — 0x24 RACTL). The bit error count is main-
tained in the RABEC2–RABEC0 registers (Section 18.39
RECEIVE PORT A BIT ERROR COUNT — 0x43 to 0x45
RABEC2 to RABEC0). This counter has no associated
threshold register and will not generate an interrupt. The
counter may be polled (read) at fixed intervals to determine
a Bit Error Rate. This counter is reset on read. The count
value is only valid when both the TXPRBS bit and the
RABEC bit are set.
Port B can operate in the same fashion using the RBBEC bit
of the RBCTL register (Section 18.44 RECEIVE PORT B
CONTROL — 0x64 RBCTL) and the RBBEC2–RBBEC0
registers (Section 18.58 RECEIVE PORT B BIT ERROR
COUNT — 0x83 to 0x85 RBBEC2 to RBBEC0).
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