DS92UT16TUF Datasheet, PDF (53/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x01
The Receive Port A Control register defines the operation of the Port A TCS DisAssembler section.
• RAESS Receive Port A, Valid Received ESS bit select. Two ESS bits are received in the Remote Alarm and Signaling Byte
as described in Section 6.3.7.1 Remote Alarm and Signaling Byte. Only one of these received bits may be designated as valid.
The valid bit is extracted and passed to the ECC transmit section as the ECC signaling bit (ESS) received on Port A. When
RAESS is set then the Remote Alarm and Signaling Byte bit[1], ESSB, is selected as valid and bit[2], ESSA is ignored. When
RAESS is clear then the Remote Alarm and Signaling Byte bit[2], ESSA, is selected as valid and bit[1], ESSB is ignored. The
names ESSA and ESSB of these bits refers to the remote receiver port from which they originated and are not associated with
the local receivers Port A and Port B. See Section 16.0 Embedded Communication Channel Operation.
• RABEC Receive Port A, Bit Error Count mode. When set the receiver expects to receive the raw scrambler PRBS pattern. See
TXPRBS bit of the TERRCTL register. The descrambler will lock to this sequence and then count individual bit errors in the
PRBS stream. This bit error count will be refiected in the RABEC2–RABEC0 registers. As there is no data cell delineation, the
frame delineation will be lost. This is not a live traffic test.
• RADFLK Receive Port A, Descrambler Force Lock. When set the descrambler will be forced out of lock and will immediately
begin to re-lock. The hardware will clear this bit and the descrambler lock status can be monitored on the RALDSLL bit of the
RALA register, see Section 18.23 RECEIVE PORT A LOCAL ALARMS — 0x22 RALA.
• RACDIS Receive Port A, Cell Discard. When set then cells with an errored HEC are discarded.
18.26 ECC RECEIVE BUFFER A — 0x26 to 0x2D ERAD7 to ERAD0
ERAD7 0x26
ERAD6 0x27
ERAD5 0x28
ERAD4 0x29
ERAD3 0x2A
ERAD2 0x2B
ERAD1 0x2C
ERAD0 0x2D
7
ERAD7[7]
ERAD6[7]
ERAD5[7]
ERAD4[7]
ERAD3[7]
ERAD2[7]
ERAD1[7]
ERAD0[7]
6
ERAD7[6]
ERAD6[6]
ERAD5[6]
ERAD4[6]
ERAD3[6]
ERAD2[6]
ERAD1[6]
ERAD0[6]
TABLE 46. ERAD7–ERAD0
5
ERAD7[5]
ERAD6[5]
ERAD5[5]
ERAD4[5]
ERAD3[5]
ERAD2[5]
ERAD1[5]
ERAD0[5]
4
ERAD7[4]
ERAD6[4]
ERAD5[4]
ERAD4[4]
ERAD3[4]
ERAD2[4]
ERAD1[4]
ERAD0[4]
3
ERAD7[3]
ERAD6[3]
ERAD5[3]
ERAD4[3]
ERAD3[3]
ERAD2[3]
ERAD1[3]
ERAD0[3]
2
ERAD7[2]
ERAD6[2]
ERAD5[2]
ERAD4[2]
ERAD3[2]
ERAD2[2]
ERAD1[2]
ERAD0[2]
1
ERAD7[1]
ERAD6[1]
ERAD5[1]
ERAD4[1]
ERAD3[1]
ERAD2[1]
ERAD1[1]
ERAD0[1]
0
ERAD7[0]
ERAD6[0]
ERAD5[0]
ERAD4[0]
ERAD3[0]
ERAD2[0]
ERAD1[0]
ERAD0[0]
Type:
Read only
Software Lock: No
Reset Value: 0x00
The ERAD7, ERAD6, ERAD5, ERAD4, ERAD3, ERAD2, ERAD1 and ERAD0 registers contain the Port A received ECC
message.
• ERAD7–ERAD0 When the ERABF bit is set then these registers contain a valid received ECC message for Port A and cannot
be overwritten by any incoming messages. When the ERABF bit is clear these registers may not contain a valid message and
should not be interpreted as such.
18.27 RECEIVE PORT A HEC COUNT — 0x2E to 0x30 RAHECC2 to RAHECC0
RAHECC2
0x2E
RAHECC1
0x2F
RAHECC0
0x30
7
RAHECC2[7]
6
RAHECC2[6]
TABLE 47. RAHECC2–RAHECC0
5
RAHECC2[5]
4
RAHECC2[4]
3
RAHECC2[3]
RAHECC1[7] RAHECC1[6] RAHECC1[5] RAHECC1[4] RAHECC1[3]
RAHECC0[7] RAHECC0[6] RAHECC0[5] RAHECC0[4] RAHECC0[3]
2
RAHECC2[2]
RAHECC1[2]
RAHECC0[2]
1
RAHECC2[1]
RAHECC1[1]
RAHECC0[1]
0
RAHECC2[0]
RAHECC1[0]
RAHECC0[0]
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The RAHECC2, RAHECC1 and RAHECC0 registers contain the Port A received errored HEC count.
• RAHECC2–RAHECC0 This register must be read in the order of most significant byte RAHECC2 first and least significant
byte RAHECC0 last or the value read will not be valid. This counter will not roll-over from 0xFFFFFF to 0x000000 but will stick
at 0xFFFFFF.
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