DS92UT16TUF Datasheet, PDF (59/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
Type:
Read/Write
Software Lock: Yes
Reset Value: 0x01
The Receive Port B Control register defines the operation of the Port B TCS DisAssembler section.
• RBESS Receive Port B, Valid Received ESS bit select. Two ESS bits are received in the Remote Alarm and Signaling Byte
as described in Section 6.3.7.1 Remote Alarm and Signaling Byte. Only one of these received bits may be designated as valid.
The valid bit is extracted and passed to the ECC transmit section as the ECC signaling bit (ESS) received on Port B. When
RBESS is set, then the Remote Alarm and Signaling Byte bit[1], ESSB, is selected as valid and bit[2], ESSA is ignored. When
RBESS is clear then the Remote Alarm and Signaling Byte bit[2], ESSA, is selected as valid and bit[1], ESSB is ignored. The
names ESSA and ESSB of these bits refers to the remote receiver port from which they originated and are not associated with
the local receivers Port A and Port B. See Section 16.0 Embedded Communication Channel Operation.
• RBBEC Receive Port B, Bit Error Count mode. When set the receiver expects to receive the raw scrambler PRBS pattern. See
TXPRBS bit of the TERRCTL register. The descrambler will lock to this sequence and then count individual bit errors in the
PRBS stream. This bit error count will be refiected in the RBBEC2–RBBEC0 registers. As there is no data cell delineation, the
frame delineation will be lost. This is not a live traffic test.
• RBDFLK Receive Port B, Descrambler Force Lock. When set the descrambler will be forced out of lock and will immediately
begin to re-lock. The hardware will clear this bit and the descrambler lock status can be monitored on the RBLDSLL bit of the
RBLA register, see Section 18.42 RECEIVE PORT B LOCAL ALARMS — 0x62 RBLA.
• RBCDIS Receive Port B, Cell Discard. When set then cells with an errored HEC are discarded.
18.45 ECC RECEIVE BUFFER B — 0x66 to 0x6D ERBD7 to ERBD0
ERBD7 0x66
ERBD6 0x67
ERBD5 0x68
ERBD4 0x69
ERBD3 0x6A
ERBD2 0x6B
ERBD1 0x6C
ERBD0 0x6D
7
ERBD7[7]
ERBD6[7]
ERBD5[7]
ERBD4[7]
ERBD3[7]
ERBD2[7]
ERBD1[7]
ERBD0[7]
6
ERBD7[6]
ERBD6[6]
ERBD5[6]
ERBD4[6]
ERBD3[6]
ERBD2[6]
ERBD1[6]
ERBD0[6]
TABLE 65. ERBD7–ERBD0
5
ERBD7[5]
ERBD6[5]
ERBD5[5]
ERBD4[5]
ERBD3[5]
ERBD2[5]
ERBD1[5]
ERBD0[5]
4
ERBD7[4]
ERBD6[4]
ERBD5[4]
ERBD4[4]
ERBD3[4]
ERBD2[4]
ERBD1[4]
ERBD0[4]
3
ERBD7[3]
ERBD6[3]
ERBD5[3]
ERBD4[3]
ERBD3[3]
ERBD2[3]
ERBD1[3]
ERBD0[3]
2
ERBD7[2]
ERBD6[2]
ERBD5[2]
ERBD4[2]
ERBD3[2]
ERBD2[2]
ERBD1[2]
ERBD0[2]
1
ERBD7[1]
ERBD6[1]
ERBD5[1]
ERBD4[1]
ERBD3[1]
ERBD2[1]
ERBD1[1]
ERBD0[1]
0
ERBD7[0]
ERBD6[0]
ERBD5[0]
ERBD4[0]
ERBD3[0]
ERBD2[0]
ERBD1[0]
ERBD0[0]
Type:
Read only
Software Lock: No
Reset Value: 0x00
The ERBD7, ERBD6, ERBD5, ERBD4, ERBD3, ERBD2, ERBD1, and ERBD0 registers contain the Port B received ECC
message.
• ERBD7–ERBD0 When the ERBBF bit is set, then these registers contain a valid received ECC message for Port B and
cannot be overwritten by any incoming messages. When the ERBBF bit is clear, these registers may not contain a valid
message and should not be interpreted as such.
18.46 RECEIVE PORT B HEC COUNT — 0x6E to 0x70 RBHECC2 to RBHECC0
RBHECC2
0x6E
RBHECC1
0x6F
RBHECC0
0x70
7
RBHECC2[7]
6
RBHECC2[6]
TABLE 66. RBHECC2–RBHECC0
5
RBHECC2[5]
4
RBHECC2[4]
3
RBHECC2[3]
RBHECC1[7] RBHECC1[6] RBHECC1[5] RBHECC1[4] RBHECC1[3]
RBHECC0[7] RBHECC0[6] RBHECC0[5] RBHECC0[4] RBHECC0[3]
2
RBHECC2[2]
RBHECC1[2]
RBHECC0[2]
1
RBHECC2[1]
RBHECC1[1]
RBHECC0[1]
0
RBHECC2[0]
RBHECC1[0]
RBHECC0[0]
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The RBHECC2, RBHECC1 and RBHECC0 registers contain the Port B received errored HEC count.
• RBHECC2–RBHECC0 This register must be read in the order of most significant byte RBHECC2 first and least significant
byte RBHECC0 or the value read will not be valid. This counter will not roll-over from 0xFFFFFF to 0x000000 but will stick at
0xFFFFFF.
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