DS92UT16TUF Datasheet, PDF (54/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

18.0 Register Description (Continued)
18.28 RECEIVE PORT A HEC THRESHOLD — 0x31 to 0x33 RAHECT2 to RAHECT0
RAHECT2
0x31
RAHECT1
0x32
RAHECT0
0x33
7
RAHECT2[7]
6
RAHECT2[6]
TABLE 48. RAHECT2–RAHECT0
5
RAHECT2[5]
4
RAHECT2[4]
3
RAHECT2[3]
2
RAHECT2[2]
RAHECT1[7] RAHECT1[6] RAHECT1[5] RAHECT1[4] RAHECT1[3] RAHECT1[2]
RAHECT0[7] RAHECT0[6] RAHECT0[5] RAHECT0[4] RAHECT0[3] RAHECT0[2]
1
RAHECT2[1]
RAHECT1[1]
RAHECT0[1]
0
RAHECT2[0]
RAHECT1[0]
RAHECT0[0]
Type:
Read/Write
Software Lock: No
Reset Value: 0xFF
The RAHECT2, RAHECT1 and RAHECT0 registers contain the Port A received erred HEC threshold. When the error count
RAHECC equals the threshold RAHECT then the RAXHEC alarm will be set.
These registers should not be set to all zeroes.
• RAHECT2–RAHECT0 Most significant byte RAHECT2 and least significant byte RAHECT0.
18.29 RECEIVE PORT A BIP COUNT — 0x34 to 0x36 RABIPC2 to RABIPC0
TABLE 49. RABIPC2–RABIPC0
RABIPC2 0x34
RABIPC1 0x35
RABIPC0 0x36
7
RABIPC2[7]
RABIPC1[7]
RABIPC0[7]
6
RABIPC2[6]
RABIPC1[6]
RABIPC0[6]
5
RABIPC2[5]
RABIPC1[5]
RABIPC0[5]
4
RABIPC2[4]
RABIPC1[4]
RABIPC0[4]
3
RABIPC2[3]
RABIPC1[3]
RABIPC0[3]
2
RABIPC2[2]
RABIPC1[2]
RABIPC0[2]
1
RABIPC2[1]
RABIPC1[1]
RABIPC0[1]
0
RABIPC2[0]
RABIPC1[0]
RABIPC0[0]
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
The RABIPC2, RABIPC1 and RABIPC0 registers contain the Port A received errored BIP count.
• RABIPC2–RABIPC0 This register must be read in the order of most significant byte RABIPC2 first and least significant byte
RABIPC0 last or the value read will not be valid. This counter will not roll-over from 0xFFFFFF to 0x000000 but will stick at
0xFFFFFF.
18.30 RECEIVE PORT A BIP THRESHOLD — 0x36 to 0x39 RABIPT2 to RABIPT0
RABIPT2 0x37
RABIPT1 0x38
RABIPT0 0x39
7
RABIPT2[7]
RABIPT1[7]
RABIPT0[7]
6
RABIPT2[6]
RABIPT1[6]
RABIPT0[6]
TABLE 50. RABIPT2–RABIPT0
5
RABIPT2[5]
RABIPT1[5]
RABIPT0[5]
4
RABIPT2[4]
RABIPT1[4]
RABIPT0[4]
3
RABIPT2[3]
RABIPT1[3]
RABIPT0[3]
2
RABIPT2[2]
RABIPT1[2]
RABIPT0[2]
1
RABIPT2[1]
RABIPT1[1]
RABIPT0[1]
0
RABIPT2[0]
RABIPT1[0]
RABIPT0[0]
Type:
Read/Write
Software Lock: No
Reset Value: 0xFF
The RABIPT2, RABIPT1 and RABIPT0 registers contain the Port A received errored BIP threshold. When the error count RABIPC
equals the threshold RABIPT then the RAXBIP alarm will be set.
These registers should not be set to all zeroes.
• RABIPT2–RABIPT0 Most significant byte RABIPT2 and least significant byte RABIPT0.
18.31 RECEIVE PORT A PERFORMANCE ALARMS — 0x3A RAPA
7
Reserved
6
Reserved
5
Reserved
Type:
Read only/Clear on Read
Software Lock: No
Reset Value: 0x00
TABLE 51. RAPA
4
Reserved
3
Reserved
2
Reserved
1
RAXHEC
0
RAXBIP
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