DS92UT16TUF Datasheet, PDF (79/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

24.0 Electrical Characteristics (Continued)
LVDS Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 14)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_DSR1
t_DRS2
Deserializer PLL Lock
Time from PWRDN (with
SYNCPAT)
Deserializer PLL Lock
Time from SYNCPAT
(Figure 28)
(Figure 29)
LVDS_ADin[+,−],
LVDS_BDin[+.,−]
t_RNM
Deserializer Noise Margin (Figure 30)
400
Max Units
30
µs
12
µs
ps
Timing Requirements for Input Clock
LVDS_TxClk, LVDS_ARefClk, LVDS_BRefClk
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 14)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_RFCP
t_RFDC
t_RFCP/t_TCP
t_RFTT
t_JIT
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to TCLK
REFCLK Transition Time
Input Jitter
(Figure 27)
Jitter Frequency < 250 kHz
Jitter Frequency < 250 kHz
Jitter Frequency < 250 kHz
19.2
40
50
−5
Max Units
ns
60
%
5
%
8
ns
15
UI
1.5
UI
0.15
UI
Microprocessor Interface Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 14)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_LLH
Low-to-High Transition
C_L = 15 pF (Figure 26)
Time
t_LHL
High-to-Low Transition
C_L = 15 pF (Figure 26)
Time
Outputs
t_SETUP
t_HOLD
See Section 17.0
Microprocessor Interface
Operation
Inputs
Max Units
6
ns
6
ns
Note 13: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are meant to imply that the devices should
be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 14: Typical values are given for V_CC = 3.3V and T_A = 25˚C
Note 15: Current into the device is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except V_OD, V_TH and
V_TL which are differential voltages.
Note 16: For the purpose of specifying deserializer P_LL performance t_DSR1 and t_DSR2 are specified with the REFCLK running and stable, and specific conditions
of the incoming data stream (SYNCPATs). t_DSR1 is the time required for the deserializer to indicate lock upon power-up or when the power-down mode. t_DSR2 is the
time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI−) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs). The time to lock to random data is dependent upon the incoming data.
Note 17: t_RNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur.
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