DS92UT16TUF Datasheet, PDF (69/86 Pages) National Semiconductor (TI) – UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

19.0 Test Features (Continued)
FIGURE 23. LOGICVISION TAP Instruction Register
The TAP controller contains a device ID register which holds
the device identification. Figure 24 shows the makeup of the
device ID register and the device ID value for the DS92UT16
device.
20031622
DEVICE ID = 0FC2801F
FIGURE 24. Device Identification Register
20031623
19.2 BOUNDARY SCAN
The DS92UT16 device contains boundary scan (BS) cells on
all inputs, outputs, bi-directs, and direction control signals.
There are no boundary scan cells on any of the inputs or
outputs from the pins to the LVDS Interface block. The
boundary scan order is shown in Table 95 along with the
type and controlling BS cell for bidirectional BS cells.For
bidirectional pins, if the controlling cell is a logic ‘1’ then they
are outputs.
TABLE 95.
No.
Pin Name
Type Ctrl.
1
RBPWDN
INPUT N/A
2
TXADEN
INPUT N/A
3
TXBDEN
INPUT N/A
4
TPWDN
INPUT N/A
5
TXSYNC
INPUT N/A
6
TXCLK
INPUT N/A
7
CPU_BUSMODE
INPUT N/A
8
CPU_CS_N
INPUT N/A
9
CPU_RD_N
INPUT N/A
10
CPU_WR_N
INPUT N/A
11
CPU_INT_N
OUTPUT N/A
12
CPU_DATA_TRI
ENABLE N/A
13
CPU_DATA_7
BIDIR 12
14
CPU_DATA_6
BIDIR 12
15
CPU_DATA_5
BIDIR 12
16
CPU_DATA_4
BIDIR 12
17
CPU_DATA_3
BIDIR 12
18
CPU_DATA_2
BIDIR 12
No.
Pin Name
Type Ctrl.
19
CPU_DATA_1
BIDIR 12
20
CPU_DATA_0
BIDIR 12
21
CPU_ADDR_7
INPUT N/A
22
CPU_ADDR_6
INPUT N/A
23
CPU_ADDR_5
INPUT N/A
24
CPU_ADDR_4
INPUT N/A
25
CPU_ADDR_3
INPUT N/A
26
CPU_ADDR_2
INPUT N/A
27
CPU_ADDR_1
INPUT N/A
28
CPU_ADDR_0
INPUT N/A
29
GPIO_TRI_3
ENABLE N/A
30
GPIO_3
BIDIR 29
31
GPIO_TRI_2
ENABLE N/A
32
GPIO_2
BIDIR 31
33
GPIO_TRI_1
ENABLE N/A
34
GPIO_1
BIDIR 33
35
GPIO_TRI_0
ENABLE N/A
36
GPIO_0
BIDIR 35
37
RESET_N
INPUT N/A
38
UTFC_MODE
ENABLE N/A
39
U_TXDATA_15
BIDIR 38
40
U_TXDATA_14
BIDIR 38
41
U_TXDATA_13
BIDIR 38
42
U_TXDATA_12
BIDIR 38
43
U_TXDATA_11
BIDIR 38
44
U_TXDATA_10
BIDIR 38
45
U_TXDATA_9
BIDIR 38
69
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