82845MP Datasheet, PDF (99/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.8.20.
PMLIMIT1 – Prefetchable Memory Limit Address Register –
Device #1
Address Offset:
Default Value:
Access:
Size:
26-27h
0000h
Read/Write, Read Only
16 bits
This register controls the host to AGP prefetchable memory accesses routing based on the following
formula:
PREFETCHABLE_MEMORY_BASE1=< address =<PREFETCHABLE_MEMORY_LIMIT1
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes when read. The
configuration software must initialize this register. For the purpose of address decode address bits
A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top
of a 1-MB aligned memory block.
Bit
Description
15:4
Prefetchable Memory Address Limit 1(PMEM_LIMIT1). Corresponds to A[31:20] of the memory
address.
Default=000h
3:0
Reserved
Note: Prefetchable memory range is supported to allow segregation by the configuration software between the
memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e.
prefetchable) from the processor perspective.
250687-002
Datasheet
99