82845MP Datasheet, PDF (117/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
Table 28. Data Bytes on SO-DIMM Used for Programming DRAM Registers
Byte
Function
2
Memory Type (SDR SDRAM or DDR SDRAM)
3
# of Row Addresses, not counting Bank Addresses
4
# of Column Addresses
5
# of SO-DIMM banks
11
ECC, no ECC
12
Refresh Rate/Type
17
# Banks on each Device
The above table is only a subset of the defined SPD bytes on the SO-DIMMs. These bytes collectively
provide enough data for programming the Intel 845MP/845MZ MCH-M SDRAM registers.
5.2.3.
5.2.3.1.
DRAM Performance Description
The overall memory performance is controlled by the DRAM timing register, which pipelines depth used
in Intel 845MP/845MZ MCH-M, memory speed grade and the type of SDRAM used in the system.
Besides this, the exact performance in a system is also dependent on the total memory supported,
external buffering and memory array layout. The most important contribution to overall performance by
the System Memory controller is to minimize the latency required to initiate and complete requests to
memory, and to support the highest possible bandwidth (full streaming, quick turn-arounds). One
measure of performance is the total flight time to complete a cache line request. A true discussion of
performance really involves the entire chipset, not just the System Memory controller.
Data Integrity (ECC)
The Intel 845MP/845MZ MCH-M supports single-bit Error Correcting Code (or Error Checking and
Correcting) and multiple-bit EC (Error Checking) on the main memory interface. The Intel
845MP/845MZ MCH-M generates an 8-bit code word for each 64-bit Qword of memory. Intel
845MP/845MZ MCH-M performs two Qword writes at a time so two 8-bit codes are sent with each
write. Since the code word covers a full Qword, writes of less than a Qword require a read-merge-write
operation. Consider a Dword write to memory. In this case, when in ECC mode, the Intel
845MP/845MZ MCH-M will read the Qword where the addressed Dword will be written, merge in the
new Dword, generate a code covering the new Qword and finally write the entire Qword and code back
to memory. Any correctable (single-bit) errors detected during the initial Qword read are corrected
before merging the new Dword. The Intel 845MP/845MZ MCH-M also supports another data integrity
mode, EC (Error Checking) mode. In this mode, the Intel 845MP/845MZ MCH-M generates and stores
a code for each Qword of memory. It then checks the code for reads from memory but does not correct
any errors that are found. Thus, the read performance hit associated with ECC is not incurred.
5.3. AGP Interface Overview
The Intel 845MP/845MZ Chipset MCH-M supports 1.5 V AGP 1x/2x/4x devices. The AGP signal
buffers are 1.5 V drive/receive (buffers are not 3.3-V tolerant). The MCH-M supports 2x/4x source
synchronous clocking transfers for read and write data, and sideband addressing. The MCH-M also
supports 1x, 2x and 4x clocking for Fast Writes initiated from the MCH-M (on behalf of the processor).
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Datasheet
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