82845MP Datasheet, PDF (98/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
R
3.8.19.
PMBASE1 – Prefetchable Memory Base Address Register –
Device #1
Address Offset:
Default Value:
Access:
Size:
24-25h
FFF0h
Read/Write, Read Only
16 bits
This register controls the host to AGP prefetchable memory accesses routing based on the following
formula:
PREFETCHABLE_MEMORY_BASE1=< address =<PREFETCHABLE_MEMORY_LIMIT1
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32-bit address. The bottom 4 bits of this register are read-only and return zeros when read. The
configuration software must initialize this register. For the purpose of address decode address bits
A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a
1-MB boundary.
Bit
Description
15:4
Prefetchable Memory Address Base 1(PMEM_BASE1). Corresponds to A[31:20] of the memory
address.
3:0
Reserved
98
Datasheet
250687-002