82845MP Datasheet, PDF (58/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
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3.7.14.
AGPM- AGP Miscellaneous Configuration
Offset:
Default:
Access:
Size:
51h
00h
Read/Write
8 bits
Bit
7:2
1
0
Description
Reserved
Aperture Access Global Enable (APEN): This bit is used to prevent access to the graphics aperture
from any port (CPU, HI_A, or AGP/PCI_B) before the aperture range is established by the
configuration software and the appropriate translation table in the main DRAM has been initialized.
The default value is "0", so this field must be set after system is fully configured in order to enable
aperture accesses.
Reserved
3.7.15.
DRB[0:7] – DRAM Row Boundary Registers – Device #0
Offset:
Default:
Access:
Size:
60-67h
00h
Read/Write
8 bits
The DRAM Row Boundary Register defines the upper boundary address of each pair of DRAM rows
with a granularity of 32 MB. Each row has its own single-byte DRB register. For example, a value of 1
in DRB0 indicates that 32 MB of DRAM has been populated in the first row.
Row0: 60h
Row1: 61h
Row2: 62h
Row3:
Row4:
Row5:
Row6:
Row7:
63h
64h **
65h **
66h **
67h **
DRB0 = Total memory in row0 (in 32MB increments)
DRB1 = Total memory in row0 + row1 (in 32MB increments)
----
DRB3 = Total memory in row0 + row1 + row2 + row3 (in 32MB increments)
** When in DDR mode DRB[4:7] must be programmed with value contained in DRB3.
Each Row is represented by a byte. Each byte has the following format.
Bit
Description
7:0
DRAM Row Boundary Address: This 8-bit value defines the upper and lower addresses for each
DRAM row. This 8-bit value is compared against a set of address lines to determine the upper
address limit of a particular row.
58
Datasheet
250687-002