82845MP Datasheet, PDF (100/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
R
3.8.21.
BCTRL1 – PCI-PCI Bridge Control Register – Device #1
Address Offset:
Default:
Access:
Size
3Eh
00h
Read Only, Read/Write
8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The
BCTRL provides additional control for the secondary interface (i.e. AGP) as well as some bits that affect
the overall behavior of the “virtual” PCI-PCI bridge embedded within MCH-M, e.g. VGA compatible
address ranges mapping.
Bit
Descriptions
7
Fast Back to Back Enable (FB2BEN): Normally this bit controls whether the bridge will generate
Fast Back to Back cycles to different targets. However, since there is only one target allowed on the
AGP interface, this bit is meaningless. This bit is hardwired to “0”.
6
Secondary Bus Reset (SRESET): MCH-M does not support generation of reset via this bit on the
AGP and therefore this bit is hardwired to “0”. Note that the only way to perform a hard reset of the
AGP bus is via the system reset either initiated by software or hardware via ICH3-M.
5
Master Abort Mode (MAMODE): This bit is hardwired to “0”. This means when acting as a master
on AGP the MCH-M will discard data on writes and return all 1s during reads when a Master Abort
occurs.
4
Reserved
3
VGA Enable (VGAEN1): Controls the routing of host initiated transactions targeting VGA compatible
I/O and memory address ranges. When this bit is set , the MCH-M will forward the following host-
initiated accesses to the AGP bus:
1) memory accesses in the range 0A0000h to 0BFFFFh
2) I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh or 3C0h to 3DFh
(inclusive of ISA address aliases - A[15:10] are not decoded)
When this bit is set, forwarding of these accesses issued by the host is independent of the I/O
address and memory address ranges that are defined by the previously defined base and limit
registers. Forwarding of these accesses is also independent of the settings of bit 2 (ISA Enable) of
this register if this bit is “1”.
If this bit is “0” (default) , then VGA compatible memory and I/O range accesses are not forwarded to
AGP. Instead they are mapped to the hub interface unless they are mapped to AGP via I/O and
memory range registers defined above (IOBASE1, IOLIMIT1, MBASE1, MLIMIT1, PMBASE1,
PMLIMIT1). Please refer to the System Address Map section of this document for further information.
2
ISA Enable (ISAEN): Modifies the response by the MCH-M to an I/O access issued by the host that
targets ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and
IOLIMIT registers. When this bit is set to 1 MCH-M will not forward to AGP any I/O transactions
addressing the last 768 bytes in each 1-KB block even if the addresses are within the range defined
by the IOBASE and IOLIMIT registers. Instead of going to AGP these cycles will be forwarded to the
hub interface. If this bit is “0” (default) then all addresses defined by the IOBASE and IOLIMIT for
host I/O transactions will be mapped to AGP.
1
Reserved
0
Parity Error Response Enable (PEREN): Controls MCH-M’s response to data phase parity errors on
AGP. G_PERR# is not implemented by the MCH-M. However, when this bit is set to 1, address and
data parity errors detected on AGP are reported via hub interface SERR# messaging mechanism, if
further enabled by SERRE1. If this bit is reset to 0, then address and data parity errors on AGP are
not reported via the MCH-M hub interface SERR# messaging mechanism. Other types of error
conditions can still be signaled via SERR# messaging independent of this bit’s state.
100
Datasheet
250687-002