82845MP Datasheet, PDF (112/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
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4.3.2.
4.4.
4.5.
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SMM Space Restrictions
If any of the following conditions are violated the results of SMM accesses are unpredictable and may
cause the system to hang:
1. The Compatible SMM space must not be set-up as cacheable.
2. High or TSEG SMM transaction address space must not overlap address space assigned to system
DRAM, the AGP aperture range, or to any “PCI” devices (including hub interface and AGP
devices). This is a BIOS responsibility.
3. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
4. When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available
DRAM. This is a BIOS responsibility.
5. Any address translated through the AGP Aperture GTLB must not target DRAM from 000A0000h
to 000FFFFFh.
I/O Address Space
The Intel 845MP/845MZ Chipset MCH-M does not support the existence of any other I/O devices beside
itself on the system bus. The MCH-M generates either hub interface A or AGP bus cycles for all
processor I/O accesses. The MCH-M contains two internal registers in the processor I/O space,
Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register
(CONFIG_DATA). These locations are used to implement configuration space access mechanism and as
described in the Configuration Register section.
The processor allows 64K+3 bytes to be addressed within the I/O space. The MCH-M propagates the
processor I/O address without any translation on to the destination bus and therefore provides
addressability for 64K+3 byte locations. Note that the upper three locations can be accessed only during
I/O address wrap-around when signal A16# address signal is asserted. A16# is asserted on the system
bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is also
asserted when an I/O access is made to 2 bytes from address 0FFFFh.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to the hub
interface A unless they fall within the AGP I/O address range as defined by the mechanisms explained
below. The MCH-M will not post I/O write cycles to IDE.
The MCH-M never responds to I/O or configuration cycles initiated on AGP or any of the hub interfaces.
Hub interface transactions requiring completion are terminated with “master abort” completion packets
on the hub interfaces. Hub interface write transactions not requiring completion are dropped. AGP/PCI
I/O reads are never acknowledged by the MCH-M.
MCH-M Decode Rules and Cross-Bridge Address
Mapping
The address map described above applies globally to accesses arriving on any of the three interfaces i.e.
Host bus, the hub interface A or AGP.
Decode Rules for the Hub Interface A
The MCH-M accepts accesses from the hub interface A with the following address ranges:
Datasheet
250687-002