82845MP Datasheet, PDF (15/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
1.1.
1.2.
System Architecture
The Intel 845MP/845MZ Chipset Memory Controller Hub-M (MCH-M) component provides the
processor interface, DRAM interface, AGP interface, and hub interface. The CPU interface supports the
Mobile Intel Pentium 4 Processor-M subset of the Extended Mode of the Scalable Bus Protocol. The
Intel 845MP/845MZ Chipset is optimized for the Mobile Intel Pentium 4 Processor-M. It supports a
single channel of DDR memory. The MCH-M contains advanced power management logic. The Intel
845MP/845MZ Chipset platform supports the third generation mobile I/O Controller Hub (ICH3-M) to
provide the features required by a mobile platform.
The Intel 845 Chipset-Mobile Family (MCH-M) is in a 593-pin FC-BGA package and contains the
following functionality:
• Supports single Mobile Intel Pentium 4 Processor-M configurations at 400 MT/s
• AGTL+ host bus with integrated termination supporting 32-bit host addressing
• 845MP supports up to 1 GB of PC2100 Memory
• 845MZ supports up to 512 MB of PC1600 Memory
• 1.5-V AGP interface with 4x SBA/PIPE# Data Transfer and Fast Write capability
• 1.8-V, 8-bit, 66-MHz 4x hub interface to ICH3-M
• Deeper Sleep
• Intel SpeedStep^® technology
• Distributed arbitration for highly concurrent operation
Mobile Intel Pentium^ 4 Processor-M Host Interface
The Intel 845MP/845MZ Chipset MCH-M is optimized for the Mobile Intel Pentium 4 Processor-M. The
primary enhancements over the Compatible Mode P6 bus protocol are:
• Source synchronous double pumped address
• Source synchronous quad pumped data
• System bus interrupt and side-band signal delivery
In this mode, the MCH-M supports a 64B cache line size. Only one processor is supported at a System
bus frequency of 400 MT/s. The MCH-M integrates AGTL+ termination resistors on all of the AGTL+
signals. The MCH-M supports 32-bit host addresses, allowing the CPU to access the entire 4 GB of the
MCH-M memory address space.
The MCH-M has a 12-deep In-Order Queue to support up to 12 outstanding pipelined address requests
on the host bus. The MCH-M supports two outstanding defer cycles at a time; however, only one to any
particular IO interface. Host initiated I/O cycles are positively decoded to AGP/PCI or MCH-M
configuration space and subtractively decoded to the hub interface. Host initiated memory cycles are
positively decoded to AGP/PCI or DRAM. AGP semantic memory accesses initiated from AGP/PCI to
DRAM are not snooped on the host bus. Memory accesses initiated from AGP/PCI using PCI semantics
and from the hub interface to DRAM will be snooped on the System bus. Memory accesses whose
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Datasheet
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