82845MP Datasheet, PDF (53/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.7.4.
PCISTS – PCI Status Register – Device #0
Address Offset:
Default Value:
Access:
Size:
06-07h
0090h
Read Only, Read/Write Clear
16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s on the hub
interface. Since MCH-M Device #0 is the host-to-hub interface A bridge, many of the bits are not
implemented.
Bit
Description
15
Reserved
14
Signaled System Error (SSE) (R/WC). This bit is set to 1 when MCH-M Device #0 generates an
SERR message over hub interface for any enabled Device #0 error condition. Device #0 error
conditions are enabled in the PCICMD and ERRCMD registers. Device #0 error flags are read/reset
from the PCISTS or ERRSTS registers. Software sets SSE to 0 by writing a 1 to this bit.
13
Received Master Abort Status (RMAS) (R/WC). This bit is set when the MCH-M generates a hub
interface request that receives a Master Abort completion packet or Master Abort Special Cycle.
Software clears this bit by writing a 1 to it.
12
Received Target Abort Status (RTAS) (R/WC). This bit is set when the MCH-M generates a hub
interface request that receives a Target Abort completion packet or Target Abort Special Cycle.
Software clears this bit by writing a 1 to it.
11
Signaled Target Abort Status (STAS) (RO). The MCH-M will not generate a Target Abort hub
interface completion packet or Special Cycle. This bit is not implemented in the MCH-M and is
hardwired to a 0. Writes to this bit position have no effect.
10:9
DEVSEL Timing (DEVT). Hub interface does not comprehend DEVSEL# protocol. These bits are
hardwired to “00”. Writes to these bit positions have no effect.
8
Master Data Parity Error Detected (DPD) (RO). PERR signaling and messaging are not
implemented by the MCH-M therefore this bit is hardwired to 0. Writes to this bit position have no
effect.
7
Fast Back-to-Back Capable (FB2B). This bit is hardwired to 1. Writes to this bit position have no
effect.
6:5
Reserved
4
Capability List (CLIST) (RO). This bit is set to 1 to indicate to the configuration software that this
device/function implements a list of new capabilities. A list of new capabilities is accessed via register
CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset pointing to the
start address within configuration space of this device where the AGP Capability standard register
resides.
3:0
Reserved
250687-002
Datasheet
53