82845MP Datasheet, PDF (121/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
PCI Command
C/BE[3:0]# Encoding
MCH-M
Cycle Destination
Response as aFRAME#
Target
Reserved
1001
Configuration Read
1010
Configuration Write
1011
Memory Read Multiple
1100
1100
Dual Address Cycle
1101
Memory Read Line
1110
1110
Memory Write and
Invalidate
1111
1111
NOTE: N/A refers to a function that is not applicable.
N/A
N/A
N/A
Main Memory
The Hub interface
N/A
Main Memory
The Hub interface
Main Memory
The Hub interface
No Response
No Response
No Response
Read
No Response
No Response
Read
No Response
Post Data
No Response
As a target of an AGP FRAME# cycle, the MCH-M only supports the following transactions:
• Memory Read. Recommended for reads of 32 bytes or less.
• Memory Read Line, and Memory Read Multiple. These commands are supported identically by the
MCH-M and allow the MCH-M to continuously supply data during MRL and MRM burst.
Recommended for reads of more than 32 bytes. The MCH-M does not support reads of the hub
interface bus from AGP.
• Memory Write and Memory Write and Invalidate. These commands are aliased and processed
identically. The MCH-M does not support writes of the hub interface bus from AGP.
• Other Commands. Other commands such as I/O R/W and Configuration R/W are not supported by
the MCH-M as a target and result in master abort.
• Exclusive Access. The MCH-M does not support PCI locked cycles as a target.
• Fast Back-to-Back Transactions. MCH-M as a target supports fast back-to-back cycles from an
AGP FRAME# initiator.
As an initiator of AGP FRAME# cycle, the MCH-M only supports the following transactions:
• Memory Read and Memory Read Line. MCH-M uses these commands to support read requests from
host to AGP. MCH-M does not support memory reads from the hub interface to AGP.
• Memory Read Multiple. This command is not supported by the MCH-M as an AGP FRAME#
initiator.
• Memory Write. MCH-M initiates AGP FRAME# write cycles on behalf of the host or the hub
interface. MCH-M does not issue Memory Write and Invalidate as an initiator. MCH-M does not
support write merging or write collapsing. MCH-M allows non-snoopable write transactions from
the hub interface to the AGP bus.
• I/O Read and Write. I/O reads and writes from the host are sent to the AGP bus if they fall within
the I/O base and limit address range for the AGP bus as programmed in the MCH-M’s PCI
configuration registers. All other host-initiated I/O accesses that do not correspond to this
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Datasheet
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