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82845MP Datasheet, PDF (120/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
Intel®82845MP/82845MZ Chipset-Mobile (MCH-M)
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Memory writes originating from the host or from the hub interface use the Fast Write protocol when it is
both capability enabled and enabled. The data rate used to perform the Fast Writes is dependent on the
bits set in the AGP Command Register bits 2:0 (DATA_RATE). If bit 2 of the
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 4x strobing. If bit 1 of
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 2x strobing. If bit 0 of
AGPCMD[DATA_RATE] field is 1, Fast Writes are disabled and data transfers occur using standard
PCI protocol. Note that only one of the three DATA_RATE bits may be set by initialization software.
This is summarized in the following table.
Table 30. Fast Write Initialization
FWEN
DATA_RATE
[2]
DATA_RATE
[1]
DATA_RATE
[0]
MCH-M =>AGP Master Write
Protocol
0
X
x
x
1
0
0
1
1
0
1
0
1
1
0
0
1x
1x
2x Strobing
4x Strobing
5.3.6. AGP FRAME# Transactions on AGP
The MCH-M accepts and generates AGP FRAME# transactions on the AGP bus. The MCH-M
guarantees that AGP FRAME# accesses to DRAM are kept coherent with the processor caches by
generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not supported.
5.3.6.1. MCH-M Target and Initiator Operations for AGP FRAME# Transactions
The following table summarizes MCH-M target operation for AGP FRAME# initiators. The only cycles
that will be claimed are memory accesses to main memory.
Table 31. PCI Commands Supported by the MCH-M When Acting as a FRAME# Target
PCI Command
C/BE[3:0]# Encoding
MCH-M
Cycle Destination
Response as aFRAME#
Target
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
0000
0001
0010
0011
0100
0101
0110
0110
0111
0111
1000
N/A
N/A
N/A
N/A
N/A
N/A
Main Memory
The Hub interface
Main Memory
The Hub interface
N/A
No Response
No Response
No Response
No Response
No Response
No Response
Read
No Response
Post Data
No Response
No Response
120
Datasheet
250687-002