82845MP Datasheet, PDF (119/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
AGP
Command
C/BE[3:0]#
Encoding
Cycle Destination
MCH-M Host Bridge
Response as PCIx Target
Reserved
1111
N/A
NOTE: N/A refers to a function that is not applicable.
No Response
As a target of an AGP cycle, the MCH-M supports all memory read and write transactions targeted at
main memory (summarized in the table above). The MCH-M supports both normal and high priority read
and write requests. The MCH-M does not support AGP cycles to the hub interface. PIPE# and SBA
cycles do not require coherency management and all AGP initiator accesses to main memory using AGP
PIPE# or SBA protocol are treated as non-snoopable cycles. These accesses are directed to the AGP
aperture in main memory that should be programmed as either uncacheable (UC) memory or write
combining (WC) in the processor’s MTRRs.
5.3.2.
AGP Transaction Ordering
The MCH-M observes transaction ordering rules as defined by the AGP Interface Specification Rev 2.0.
5.3.3.
AGP Signal Levels
The 1x/2x/4x data transfers use 1.5-V signaling levels as described in the AGP 2.0 specification.
5.3.4.
4x AGP Protocol
In addition to the 1x and 2x AGP protocol, the MCH-M supports 4x AGP read and write data transfers
and 4x sideband address. The 4x operation is compliant with the AGP 2.0 specification.
The MCH-M indicates that it supports 4x data transfers through RATE[2] (bit 2) of the AGP Status
Register. When DATA_RATE[2] of the AGP Command Register is set to 1 during system initialization,
the MCH-M performs AGP read/write data transactions using 4x protocol. This bit is not dynamic. Once
this bit is set during initialization, the data transfer rate may not be changed.
The 4x data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4x data
transfer protocol is identical to 1x/2x protocol. In 4x mode 16 bytes of data are transferred on every 66-
MHz clock edge. The minimum throttleable block size remains four 66-MHz clocks, which means 64
bytes of data are transferred per block. Three additional signal pins are required to implement the 4x data
transfer protocol. These signal pins are complementary data transfer strobes for the AD bus (2) and the
SBA bus (1).
5.3.5. Fast Writes
MCH-M supports 2x and 4x Fast Writes from the MCH-M to the graphics controller on AGP. Fast Write
operation is compliant with the AGP 2.0 specification.
The MCH-M will not generate Fast Back to Back (FB2B) cycles in 1x mode, but will generate FB2B
cycles in 2x and 4x Fast Write modes.
To use the Fast Write protocol, the Fast Write Enable configuration bit, AGPCMD[FWEN] (bit 4 of the
AGP Command Register), must be set to 1.
250687-002
Datasheet
119