82845MP Datasheet, PDF (143/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^® 845MZ Chipset:82845MZ (MCH-M)
R
9.4. Testability
In the MCH-M, testability for Automated Test Equipment (ATE) board level testing has been implemented
as and XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it. Refer to
Figure 11 for an example XOR chain.
Figure 11. XOR–Tree Chain
VCC1_8
XOR
Out
9.4.1.
Input
Input
Input
Input
Input
xor.vsd
The algorithm used for in –circuit test is as follows
• Drive all input pins to an initial logic level ‘1’. Observe the output corresponding to scan chain being
tested.
• Toggle pins one at a time starting from the first pin in the chain, continuing to the last pin, from its
initial logic level to the opposite logic level. Observe the output changes with each pin toggle.
XOR Test Mode Initialization
XOR test mode can be entered by pulling three shared pins (reset straps) low through the rising transition
of RSTINB. The signals that need to be pulled are as follows:
GGNTB = 0 (Global strap enable)
SBA[1] = 0 (XOR strap)
ST[2] = 0 (PLL Bypass mode; it is recommended to enter PLL Bypass in XOR test mode)
250687-001
Datasheet
143