82845MP Datasheet, PDF (85/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.8. AGP Bridge Registers – Device #1
Table 24 shows the access attributes for configuration space.
Table 24. Nomenclature for Access Attributes
RO
Read Only. If a register is read only, writes to this register have no effect.
R/W
Read/Write. A register with this attribute can be read and written.
R/WC
Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1
clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
Table 25 summarizes the MCH-M configuration space for Device #1.
Table 25. MCH-M Configuration Space - Device #1
Address Offset Register Symbol
Register Name
00-01h
02-03h
04-05h
06-07h
08
09
0Ah
0Bh
0Ch
0Dh
0Eh
0F-17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1E-1Fh
20-21h
22-23h
24-25h
VID1
DID1
PCICMD1
PCISTS1
RID1
SUBC1
BCC1
MLT1
HDR1
PBUSN1
SBUSN1
SUBUSN1
SMLT1
IOBASE1
IOLIMIT1
SSTS1
MBASE1
MLIMIT1
PMBASE1
Vendor Identification
Device Identification
PCI Command Register
PCI Status Register
Revision Identification
Reserved
Sub-Class Code
Base Class Code
Reserved
Master Latency Timer
Header Type
Reserved
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Bus Master Latency
Timer
I/O Base Address Register
I/O Limit Address Register
Secondary Status Register
Memory Base Address Register
Memory Limit Address Register
Prefetchable Memory Base
Address Reg.
Default Value
8086h
1A31hh
0000h
00A0h
Silicon Revision
Access
RO
RO
RO, R/W
RO, R/WC
RO
04h
RO
06h
RO
00h
RO, R/W
01h
RO
00h
00h
00h
00h
F0h
00h
02A0h
FFF0h
0000h
FFF0h
RO
R/W
R/W
RO, R/W
RO, R/W
RO, R/W
RO, R/WC
RO, R/W
RO, R/W
RO, R/W
250687-002
Datasheet
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