82845MP Datasheet, PDF (61/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.7.18.
DRC – DRAM Controller Mode Register – Device #0
Offset:
Default:
Access:
Size:
7C-7Fh
00000000h
Read/Write
32 bits
Bit
31:30
29
28
27:24
23:22
21:20
19:11
10:8
7
Description
Revision Number (REV): Reflects the revision number of the format used for DDR register
definition. Currently, this field must be “00”, since this (rev “00”) is the only existing version of the
specification.
Initialization Complete (IC): This bit is used for communication of software state between the
memory controller and the BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory
array is complete.
Dynamic Power-down mode Enable: When set, the DRAM controller will put pair of rows into
power down mode when all banks are pre-charged (closed). Once a bank is accessed, the relevant
pair of rows is taken out of Power Down mode.
The entry into power down mode is performed by de-activation of CKE. The exit is performed by
activation of CKE.
0: DRAM Power-down disabled
1: DRAM Power-down enabled
Active DDR Rows: Implementations may use this field to limit the maximum number of DDR rows
that may be active at once.
0000
All rows allowed to be in the active state
Others: Reserved.
Reserved
DRAM Data Integrity Mode (DDIM): These bits select one of 4 DRAM data integrity modes.
DDIM Operation
00
Non-ECC mode
10
Error checking with correction.
Other
Reserved
Reserved
Refresh Mode Select (RMS): This field determines whether refresh is enabled and, if so, at what
rate refreshes will be executed.
000:
001:
010:
011:
111:
Other:
Refresh disabled
Refresh enabled. Refresh interval 15.6 µSec
Refresh enabled. Refresh interval 7.8 µsec
Refresh enabled. Refresh interval 64 µsec
Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Reserved
Reserved
250687-002
Datasheet
61