82845MP Datasheet, PDF (72/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
R
3.7.26.
AGPSTAT – AGP Status Register – Device #0
Address Offset:
Default Value:
Access:
Size:
A4-A7h
1F00_0217h
Read Only
32 bits
This register reports AGP device capability/status.
Bit
31:24
23:10
9
8:6
5
4
3
2:0
Description
Request Queue (RQ): This field is hardwired to 1Fh to indicate a maximum of 32 outstanding AGP
command requests can be handled by the MCH-M. This field contains the maximum number of AGP
command requests the MCH-M is configured to manage.
Default =1Fh to allow a maximum of 32 outstanding AGP command requests.
Reserved
Side Band Addressing Support (SBA): This bit indicates that the MCH-M supports side band
addressing. It is hardwired to 1.
Reserved
Greater that 4 GB Support (4GB): This bit indicates that the MCH-M does not support addresses
greater than 4 gigabytes. It is hardwired to 0.
Fast Write Support (FW): This bit indicates that the MCH-M supports Fast Writes from the host to
the AGP master. It is hardwired to a 1.
Reserved
Data Rate Support (RATE): After reset the MCH-M reports its data transfer rate capability. Bit 0
identifies if MCH-M supports 1x data transfer mode, bit 1 identifies if MCH-M supports 2x data
transfer mode, and bit 2 identifies if MCH-M supports 4x data transfer mode. 1x, 2x, and 4x data
transfer modes are supported by the MCH-M and therefore this bit field has a Default Value = 111.
Note that the selected data transfer mode applies to both AD bus and SBA bus. It also applies to Fast
Writes if they are enabled.
72
Datasheet
250687-002