82845MP Datasheet, PDF (73/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.7.27.
AGPCMD – AGP Command Register – Device #0
Address Offset:
Default Value:
Access:
Size:
A8-ABh
0000_0000h
Read/Write, Read Only
32 bits
This register provides control of the AGP operational parameters.
Bit
31:10
9
8
7:5
4
3
2:0
Description
Reserved
SBA Enable (SBAEN): When this bit is set to 1, the side band addressing mechanism is enabled.
AGP Enable (AGPEN): When this bit is reset to 0, the MCH-M will ignore all AGP operations,
including the sync cycle. Any AGP operations received while this bit is set to 1 will be serviced even if
this bit is subsequently reset to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of
an SBA command being delivered in 1X mode the command will be issued.
0 = MCH-M will ignore all AGP operations, including the sideband strobe sync cycle.
1 = MCH-M will respond to AGP operations delivered via PIPE#, or to operations delivered via SBA if
the AGP Side Band Enable bit is also set to 1.
Reserved
FW Enable (FWEN): When this bit is set, the MCH-M will use the Fast Write protocol for Memory
Write transactions from the MCH-M to the AGP master. Fast Writes will occur at the data transfer
rate selected by the data rate bits (2:0) in this register. When this bit is cleared, or when the data rate
bits are set to 1x mode, the Memory Write transactions from the MCH-M to the AGP master use
standard PCI protocol.
Reserved
Data Rate (DRATE): The settings of these bits determine the AGP data transfer rate. One (and only
one) bit in this field must be set to indicate the desired data transfer rate.
Encoding Description
001
010
100
1x transfer mode
2x transfer mode
4x transfer mode
Configuration software will update this field by setting only one bit that corresponds to the capability of
AGP master (after that capability has been verified by accessing the same functional register within
the AGP masters’ configuration space.)
NOTE: This field applies to G_AD and SBA buses. It also applies to Fast Writes if they are enabled.
250687-002
Datasheet
73