82845MP Datasheet, PDF (95/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.8.16.
SSTS1 – Secondary PCI-PCI Status Register – Device #1
Address Offset:
Default Value:
Access:
Size:
1E-1Fh
02A0h
Read Only, Read/Write Clear
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary
side (i.e. AGP side) of the “virtual” PCI-PCI bridge embedded within MCH-M.
Bit
Descriptions
15
Detected Parity Error (DPE1): This bit is set to a 1 to indicate MCH-M’s detection of a parity error in
the address or data phase of AGP bus transactions. Software sets DPE1 to 0 by writing a 1 to this bit.
14
Reserved
13
Received Master Abort Status (RMAS1): When the MCH-M terminates a Host-to-AGP with an
unexpected master abort, this bit is set to 1. Software resets this bit to 0 by writing a 1 to it.
12
Received Target Abort Status (RTAS1): When an MCH-M-initiated transaction on AGP is
terminated with a target abort, RTAS1 is set to 1. Software resets RTAS1 to 0 by writing a 1 to it.
11
Signaled Target Abort Status (STAS1): STAS1 is hardwired to a 0, since the MCH-M does not
generate target abort on AGP.
10:9
DEVSEL# Timing (DEVT1): This 2-bit field indicates the timing of the DEVSEL# signal when the
MCH-M responds as a target on AGP, and is hardwired to the value 01b (medium) to indicate the
time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.
8
Master Data Parity Error Detected (DPD1): Hardwired to 0. MCH-M does not implement G_PERR#
signal.
7
Fast Back-to-Back Capable (FB2B1): This bit is hardwired to 1, since MCH-M as a target supports
fast back-to-back transactions to different targets on the AGP interface.
6
Reserved
5
66 MHz Capable (CAP66): This bit is hardwired to 1 to indicate that AGP bus is capable of 66-MHz
operation.
4:0
Reserved
250687-002
Datasheet
95