82845MP Datasheet, PDF (88/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
R
3.8.3.
PCICMD1 – PCI-PCI Command Register – Device #1
Address Offset:
Default:
Access:
Size
04-05h
0000h
Read Only, Read/Write
16 bits
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Descriptions
Reserved
Fast Back-to-Back Enable (FB2BEn): Not Applicable. Hardwired to “0.”
SERR Message Enable (SERRE1): This bit is a global enable bit for Device #1 SERR messaging.
The MCH-M does not have an SERR# signal. The MCH-M communicates the SERR# condition by
sending an SERR message to the ICH3-M. If this bit is set to a 1, the MCH-M is enabled to generate
SERR messages over the hub interface for specific Device #1 error conditions that are individually
enabled in the BCTRL register. The error status is reported in the PCISTS1 register. If SERRE1 is
reset to 0, then the SERR message is not generated by the MCH-M for Device #1.
NOTE: This bit only controls SERR messaging for the Device #1. Device #0 has its own SERRE bit to
control error reporting for error conditions occurring on Device #0.
Address/Data Stepping (ADSTEP): Not applicable. Hardwired to “0.”
Parity Error Enable (PERRE1): Parity checking is not supported on the primary side of this device.
Hardwired to ‘0’
Reserved
Memory Write and Invalidate Enable (MWIE): This bit is implemented as Read Only and returns a
value of 0 when read.
Special Cycle Enable (SCE): This bit is implemented as Read Only and returns a value of 0 when
read.
Bus Master Enable (BME1): This bit is not functional. It is a RW bit for compatibility with compliance
testing software.
Memory Access Enable (MAE1): This bit must be set to 1 to enable the Memory and Prefetchable
memory address ranges defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
When set to 0 all of device #1’s memory space is disabled.
I/O Access Enable (IOAE1): This bit must be set to1 to enable the I/O address range defined in the
IOBASE1, and IOLIMIT1 registers. When set to 0 all of device #1’s I/O space is disabled.
88
Datasheet
250687-002