82845MP Datasheet, PDF (55/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.7.8.
MLT – Master Latency Timer Register – Device #0
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
Read Only
8 bits
The hub interface does not comprehend the concept of Master Latency Timer. Therefore, this register is
not implemented.
3.7.9.
Bit
Description
7:0
These bits are hardwired to 0. Writes have no effect.
HDR – Header Type Register – Device #0
Offset:
Default:
Access:
Size:
0Eh
00h
Read Only
8 bits
This register identifies the header layout of the configuration space. No physical register exists at this
location.
Bit
Description
7:0
This read only field always returns 0 when read and writes have no effect.
250687-002
Datasheet
55