82845MP Datasheet, PDF (92/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
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3.8.10.
PBUSN1 – Primary Bus Number Register – Device #1
Offset:
Default:
Access:
Size:
18h
00h
Read Only
8 bits
This register identifies that “virtual” PCI-PCI Bridge is connected to bus #0.
Bit
7:0
Bus Number. Hardwired to “0.”
Descriptions
3.8.11.
SBUSN1 – Secondary Bus Number Register – Device #1
Offset:
Default:
Access:
Size:
19h
00h
Read /Write
8 bits
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-PCI bridge
i.e. to AGP. This number is programmed by the PCI configuration software to allow mapping of
configuration cycles to AGP.
Bit
Descriptions
7:0
Bus Number. Programmable. Default = “00h”.
3.8.12.
SUBUSN1 – Subordinate Bus Number Register – Device #1
Offset:
Default:
Access:
Size:
1Ah
00h
Read /Write
8 bits
This register identifies the subordinate bus (if any) that resides at the level below AGP. This number is
programmed by the PCI configuration software to allow mapping of configuration cycles to AGP.
Bit
Descriptions
7:0
Bus Number. Programmable. Default = “00h”.
92
Datasheet
250687-002