82845MP Datasheet, PDF (30/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
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2.5. Clocks, Reset, and Miscellaneous
Table 12. Clocks, Reset, and Miscellaneous Descriptions
Signal Name
Type
Description
BCLK /
BCLK#
66IN
SCK[5:0]
SCK#[5:0]
RSTIN#
TESTIN#
I
CMOS
I
CMOS
O
CMOS
O
CMOS
I
CMOS
I
CMOS
Differential Host Clock In: These pins receive a differential host clock from the
external clock synthesizer. This clock is used by all of the MCH-M logic that is in
the Host clock domain.
66-MHz Clock In: This pin receives a 66-MHz clock from the clock synthesizer.
This clock is used by AGP/PCI and hub interface clock domains.
Note: That this clock input is 3.3-V tolerant.
SDRAM Differential Clock (DDR): These signals deliver a source synchronous
clock to the SO-DIMMs. There are three per SO-DIMM.
SDRAM Inverted Differential Clock (DDR): These signals are the complement to
the SCK[5:0] signals. There are three per SO-DIMM.
Reset In: When asserted this signal will asynchronously reset the MCH-M logic.
This signal is connected to the PCIRST# output of the ICH3-M. All AGP/PCI output
and bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1
specifications.
Note: That this input needs to be 3.3-V tolerant.
Test Input: This pin is used for manufacturing and board level test purposes.
Note: This signal has an internal pullup resistor.
30
Datasheet
250687-002