82845MP Datasheet, PDF (79/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.7.33.
TOM – Top of Low Memory Register – Device #0
Address Offset:
Default Value:
Access:
Size:
C4-C5h
0100h
Read/Write
16 bits
This register contains the maximum address below 4 GB that should be treated as a memory access. Note
that this register must be set to a value of 0100h (16 MB) or greater. Usually it will sit below the areas
configured for the hub interface, PCI memory, and the graphics aperture.
Bit
Description
15:4
Top of Low Memory (TOM): This register contains the address that corresponds to bits 31 to 20 of
the maximum DRAM memory address that lies below 4 GB. Configuration software should set this
value to either the maximum amount of memory in the system or to the minimum address allocated
for PCI memory or the graphics aperture, whichever is smaller.
Programming example: 400h = 1 GB. An access to 4000_0000h or above will be considered above
the TOM and therefore not routed to DRAM. It may go to AGP, aperture, or subtractively decode to
Hub Interface.
3:0
Reserved
250687-002
Datasheet
79