82845MP Datasheet, PDF (43/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.6.1.
DRAMWIDTH—DRAM Width Register
Address Offset:
Default Value:
Access:
Size:
2Ch
00h
R/W
8 bits
This register determines the width of SDRAM devices populated in each row of memory.
Bit
Descriptions
7:4
Reserved.
3
Row 3 Width. Width of devices in Row 3
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
2
Row 2 Width. Width of devices in Row 2
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
1
Row 1 Width. Width of devices in Row 1
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
0
Row 0 Width. Width of devices in Row 0
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Note: Since there are multiple clock signals assigned to each row of a DIMM, it is important to clarify exactly
which row width field affects which clock signal.
Row Parameters
0
1
2
3
DDR Clocks Affected
SCK[2:0]/SCK[2:0]#
SCK[2:0]/SCK[2:0]#
SCK[5:3]/SCK[5:3]#
SCK[5:3]/SCK[5:3]#
250687-002
Datasheet
43