82845MP Datasheet, PDF (123/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
5.4.1. Various States
Table 32. Power Management State Combinations
Global (G) Sleep (S) CPU (C)
state
State
State
CPU
Clock
(FCLK)
MCH-M
Host Clock
(DCLK)
System Memory
G0
S0
C0
On
G0
S0
C1
On
G0
S0
C2
On
G0
S0
C3
Off
G0
S0
C4
Off
G1
S1M
N/A
Off
G1
S3
N/A
Off
G1
S4
N/A
Off
G2
S5
N/A
Off
G3
N/A
N/A
Off
On
On
On
On
On
On
On
PwrDown Self Refresh
On
PwrDown Self Refresh
Off
PwrDown Self Refresh
Off
PwrDown Self Refresh
Off
PwrDown Self Refresh
Off
PwrDown Self Refresh
Off
Off
Processor State
Full On
Auto-Halt
Stop Grant
Deep Sleep
DeepER Sleep
5.4.2.
General Description of Supported CPU States
• C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK# is
deasserted and the processor core is active. The processor can service snoops and maintain cache
coherency in this state.
• C1 (Auto Halt): The first level of power reduction occurs when the processor executes an Auto-
Halt instruction. This stops the execution of the instruction stream and reduces the processor’s
power consumption. The processor can service snoops and maintain cache coherency in this state.
• C2 (Stop Grant): To enter this low power state, STPCLK# is asserted. The processor can still
service snoops and maintain cache coherency in this state.
• C3 (Sleep or Deep Sleep): In these states the processor clock is stopped. The MCH-M assumes
that no AGP, AGP/PCI, or HubLink cycles (except special cycles) will occur while the MCH-M is
in this state. The processor cannot snoop its caches to maintain coherency while in the C3 state.
• C4 (DeepER Sleep): The C4 state appears to Intel 845MP/845MZ as identical to the C3 state, but
in this state the processor core voltage is lowered. There are no internal events in Intel
845MP/845MZ for the C4 state that differ from the C3 state.
250687-002
Datasheet
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