82845MP Datasheet, PDF (97/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.8.18.
MLIMIT1 – Memory Limit Address Register – Device #1
Address Offset:
Default Value:
Access:
Size:
22-23h
0000h
Read/Write, Read Only
16 bits
This register controls the host to AGP non-prefetchable memory accesses routing based on the following
formula:
MEMORY_BASE1=< address =<MEMORY_LIMIT1
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32-bit address. The bottom 4 bits of this register are read-only and return zeros when read. The
configuration software must initialize this register. For the purpose of address decode address bits
A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top
of a 1-MB aligned memory block.
Bit
Description
15:4
Memory Address Limit 1(MEM_LIMIT1). Corresponds to A[31:20] of the memory address.
Default=000h
3:0
Reserved
Note:
The memory range covered by MBASE1 and MLIMIT1 registers are used to map non-prefetchable AGP
address ranges (typically where control/status memory-mapped I/O data structures of the graphics
controller will reside), and PMBASE 1and PMLIMIT1 are used to map prefetchable address ranges
(typically graphics local memory). This segregation allows application of USWC space attribute to be
performed in a true plug-and-play manner to the prefetchable address range for improved host-AGP
memory access performance.
250687-002
Datasheet
97