82845MP Datasheet, PDF (38/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
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AGP Configuration Mechanism
From the chipset configuration perspective, AGP is seen as a PCI bus interface residing on a Secondary
Bus side of the “virtual” PCI-PCI bridges referred to as the MCH-M Host-AGP bridge. On the Primary
Bus side, the “virtual” PCI-PCI bridge is attached to PCI Bus #0. Therefore, the PRIMARY BUS
NUMBER register is hardwired to “0”. The “virtual” PCI-PCI bridge entity converts Type #1 PCI Bus
Configuration cycles on PCI Bus #0 into Type 0 or Type 1 configuration cycles on the AGP interface.
Type 1 configuration cycles on PCI Bus #0 that have a BUS NUMBER that matches the SECONDARY
BUS NUMBER of the MCH-M’s “virtual” Host-to-PCI_B/AGP bridge will be translated into Type 0
configuration cycles on the AGP interface.
If the Bus Number is non-zero, greater than the value programmed into the SECONDARY BUS
NUMBER register, and less than or equal to the value programmed into the SUBORDINATE BUS
NUMBER register, the MCH-M will generate a Type 1 PCI configuration cycle on AGP.
MCH-M Register Introduction
The MCH-M contains two sets of software accessible registers, accessed via the Host CPU I/O address
space:
1. Control registers I/O mapped into the CPU I/O space, which control access to PCI and AGP
configuration space (see section entitled I/O Mapped Registers).
2. Internal configuration registers residing within the MCH-M are partitioned into four logical device
register sets (“logical” since they reside within a single physical device). The first register set is
dedicated to Host-HI Bridge functionality (i.e. DRAM configuration, other chip-set operating
parameters and optional features). The second register block is dedicated to Host-AGP Bridge
functions (controls AGP interface configurations and operating parameters).
The MCH-M supports PCI configuration space accesses using the mechanism denoted as Configuration
Mechanism #1 in the PCI specification.
The MCH-M internal registers (I/O Mapped and Configuration registers) are accessible by the Host
CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the
exception of CONFIG_ADDRESS, which can only be accessed as a Dword. All multi-byte numeric
fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field).
Reserved Bits:
Some of the MCH-M registers described in this section contain reserved bits. These bits are labeled
"Reserved”. Software must deal correctly with fields that are reserved. On reads, software must use
appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of
reserved bit positions must first be read, merged with the new values for other bit positions and then
written back. Note the software does not need to perform read, merge, and write operation for the
configuration address register.
Reserved Registers:
In addition to reserved bits within a register, the MCH-M contains address locations in the configuration
space of the Host-HI Bridge entity that are marked either "Reserved" or “Intel Reserved”. When a
Datasheet
250687-002