82845MP Datasheet, PDF (22/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
R
Signal Name
HD[63:0]#
HDSTBP[3:0]#
HDSTBN[3:0]#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
RS[2:0]#
Type
I/O
AGTL+ 4x
I/O
AGTL+ 4x
I/O
AGTL+
I/O
AGTL+
I
AGTL+
I/O
AGTL+ 2x
O
AGTL+
O
AGTL+
Description
Host Data: These signals are connected to the system data bus. HD[63:0]# are
transferred at 4x rate. Note that the data signals are inverted on the system bus.
Differential Host Data Strobes: The differential source synchronous strobes used
to transfer HD[63:0]# and DBI[3:0]# at the 4x transfer rate.
Strobe
HDSTBP3#, HDSTBN3#
HDSTBP2#, HDSTBN2#
HDSTBP1#, HDSTBN1#
HDSTBP0#, HDSTBN0#
Data Bits
HD[63:48]#, DBI3#
HD[47:32]#, DBI2#
HD[31:16]#, DBI1#
HD[15:0]#, DBI0#
Hit: Indicates that a caching agent holds an unmodified version of the requested
line. Also, driven in conjunction with HITM# by the target to extend the snoop
window.
Hit Modified: Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line.
Also, driven in conjunction with HIT# to extend the snoop window.
Host Lock: All system bus cycles sampled with the assertion of HLOCK# and
ADS#, until the negation of HLOCK# must be atomic, i.e. no hub interface or
AGP snoopable access to DRAM are allowed when HLOCK# is asserted by the
processor.
Host Request Command: Defines the attributes of the request. In Enhanced
Mode HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting agent
during both halves of Request Phase. In the first half the signals define the
transaction type to a level of detail that is sufficient to begin a snoop request. In the
second half the signals carry additional information to define the complete
transaction type.
The transactions supported by the MCH-M Host Bridge are defined in the Host
Interface section of this document.
Host Target Ready: Indicates that the target of the processor transaction is able
to enter the data transfer phase.
Response Status: Indicates type of response according to the following the table:
RS[2:0]
000
001
010
011
100
101
110
111
Response type
Idle state
Retry response
Deferred response
Reserved (not driven by MCH-M)
Hard Failure (not driven by MCH-M)
No data response
Implicit Write back
Normal data response
22
Datasheet
250687-002